Z80_Timings_on_AMSTRAD_CPC_Cheat_sheet.pdf
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Z80 CPC Timings cheat sheet - Introduction
Z80 timings on Amstrad CPC - Cheat sheet
This document is a visual layout made by cpcitor/findyway from data at
http://www.cpctech.org.uk/docs/instrtim.html
Instruction timings
The main clock in the CPC is 16Mhz This is provided to
the Gate-Array which generates the other clocks.
The Gate Array has the following roles:
generation of a 1Mhz clock for the CRTC and AY-3-8912
generation of a 4Mhz clock for the CPU
arbitrates access to the RAM between the CPU and the
video hardware (CRTC and Gate-Array)
Every microsecond:
The CRTC generates a memory address using it's MA
and RA signal outputs
The Gate-Array fetches two bytes for each address
The video hardware is given priority so that the display is
not disrupted
The Gate-Array generates the "READY" signal which is
connected to the "/WAIT" input signal of the CPU. This
signal is used to stop the CPU accessing while the
video-hardware is accessing it. As a result, all instruction
timings are stretched so that they are all multiples of a
microsecond (1µs), and this gives an effective CPU clock
of 3.3Mhz.
.
Key:
.
Other timings
Time between acknowledge of a
interrupt and execution of a interrupt
Mode 0: (depends on instruction)
Mode 1: 5
Mode 2: 19
1 monitor scanline: 64 microseconds
1 50Hz monitor frame: 19968
microseconds.
cc
r
b
n
nnnn
dd
rp
nc
c
condition code (z,nz,c,nc,p,m,po,pe)
8-bit register (B,C,D,E,H,L,A)
Bit number (0,1,2,3,4,5,6,7)
8 bit value
16 bit value
8 bit displacement
16-bit register (HL,DE,BC) or SP
(except for PUSH and POP)
condition not satisfied
condition satisfied
NOTES:
(note 1) This timing applies when
there are multiple DD or FD prefix's
together.
The timings for IY index register pair
are identical to the timings for IX
register pair.
The table on next page gives the complete execution time for all CPU instructions
These timings have been measured
Page 1
Z80 CPC Timings cheat sheet - timings
1 NOP
.
2 NOPs
ADD A,HIX
ADC A,HIX
SUB HIX
SBC A,HIX
AND HIX
XOR HIX
OR HIX
CP HIX
ADD A,n
ADC a,n
SUB n
SBC A,n
AND n
XOR n
OR n
CP n
.
ADD HL,rp
3 NOPs
.
ADD IX,rp
4 NOPs
SBC HL,rp
ADC HL,rp
.
5 NOPs
ADD A,(IX+dd)
ADC A,(IX+dd)
SUB (IX+dd)
SBC A,(IX+dd)
AND (IX+dd)
XOR (IX+dd)
OR (IX+dd)
CP (IX+dd)
CPD
.
6 NOPs
.
7 NOPs
ARITHMETIC & LOGIC
ADD A,r
ADD A,(HL)
ADC A,r
ADC A,(HL)
SUB r
SUB A,(HL)
SBC A,r
SBC A,(HL)
AND r
AND (HL)
XOR r
XOR (HL)
OR r
OR (HL)
CP r
CP (HL)
RLCA
RRCA
RLA
RRA
RLC r
RRC r
RR r
RL r
SLA r
SLL r
SRL r
CPI
RLC (IX+dd)
RRC (IX+dd)
RL (IX+dd)
RR (IX+dd)
SLA (IX+dd)
SRA (IX+dd)
SLL (IX+dd)
SRL (IX+dd)
RLC (HL)
RRC (HL)
RR (HL)
RL (HL)
SLA (HL)
SLL (HL)
SRL (HL)
RLD
RRD
BITS, FLAGS & SPECIAL ARITHMETIC
SCF
BIT b,r
CCF
RES b,r
CPL
SET b,r
DAA
NEG
INCR & DECR
INC r
INC rp
DEC r
DEC rp
LOAD
LD r,r
LD A,(BC)
LD (BC),A
LD (DE),A
LD A,(DE)
LD r,(HL)
LD (HL),r
LOAD WITH PC a.k.a. JUMPS
JP (HL)
JP (IX)
JR cc,dd
nc : 2, c : 3
LD r,HIX
LD r,LIX
LD HIX,r
LD LIX,r
LD r,n
BIT b,(HL)
RES b,(HL)
SET b,(HL)
BIT r,(IX+dd)
RES r,(IX+dd)
SET r,(IX+dd)
INC HIX
DEX HIX
INC LIX
DEC LIX
INC (HL)
DEC (HL)
INC IX
DEC IX
LD (nnnn),rp
LD rp,(nnnn)
(includes LD (nnnn),HL
and LD (nnnn),HL
with ED prefix)
INC (IX+dd)
DEC (IX+dd)
LD (HL),nn
LD HIX,nn
LD LIX,nn
LD rp,nnnn
LD I,A
LD A,I
LD R,A
LD A,R
LD A,(nnnn)
LD (nnnn),A
LD IX,nnnn
LD (nnnn),HL
LD HL,(nnnn)
LD r,(IX+dd)
LD (IX+dd),r
LDI
LDD
LD (IX+dd),nn
LD (nnnn),IX
LD IX,(nnnn)
JP nnnn
JP cc,nnnn
JR dd
RET
DJNZ dd
RETN
RETI
b-1=0 : 3, b-1<>0 : 4
PUSH/POP/LOAD WITH SP/CALL/RET
POP rp
LD SP,HL
IN/OUT, SPECIAL
NOP
ED "nop" (ED 00 - ED 3F)
HALT
IM 0
EX AF,AF'
IM 1
EX DE,HL
IM 2
EXX
DI,EI
DD/FD
Prefix (note 1)
LD SP,IX
PUSH rp
RET cc
Nc : 2, c : 4
CALL nnnn
PUSH IX
PUSH IY
CALL cc,nnnn
Nc : 3, c : 5
POP IX
POP IY
EX (SP),HL
EX (SP),IX
IN A,(nn)
OUT (nn),A
IN r,(C)
OUT (C),r
IN F,(C)
OUT (C),0
RST 0
RST 1
RST 2
RST 3
OUTI
OUTD
IND
INI
LDIR, LDDR
CPDR
CPIR
BC-1=0 : 5, BC-1<>0 : 6
BC-1=0 : 5, BC-1<>0 : 6
BC-1=0 : 5, BC-1<>0 : 6
BC-1=0 : 5, BC-1<>0 : 6
RST 4
RST 5
RST 6
RST 7
INDR, INIR
OTDR, OTIR
Page 2
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