The 68000's Instruction Set_eng.pdf

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The
68000's
Instruction
Set
W
e
have
included
this
appendix
to
save
you
the
task
of
having
to
turn
to
secondary
materiał
when
writing
68000
assembly
language
programs.
Since
most
programmers
are
not
interested
in
the
encoding
of
instructions,
details
of
instruction
encoding
have
been
omitted
(i.e.,
the
actual
op-code
bit
patterns).
Applications
of
some
of the
instructions
have
been
provided
to
demonstrate
how
they
can
be
used
in
practice.
Instructions
are
listed
by
mnemonic
in
alphabetical
order.
The
information
provided
about
each
instruction
is:
its
assembler
syntax,
its
attributes
(i.e.,
whether
it
takes
a
byte,
word,
or
longword
operand),
its
description
in
words,
the
effect
its
execution
has
on
the
condition
codes,
and
the
addressing
modes
it
may
take.
The
effect
of
an
instruction
on
the
CCR
is
specified
by
the
following
codes:
U
The
state
of
the
bit
is
undefined
(i.e.,
its
value
cannot
be
predicted)
-
The
bit
remains
unchanged
by
the
execution
of
the
instruction
*
The
bit
is
set
or
cleared
according
to
the
outcome
of
the
instruction.
Unless
an
addressing
mode
is
implicit
(e.g.,
NOP
,
RESET
,
RTS
,
etc.),
the
legal
source
and
destination
addressing
modes
are
specified
by
their
assembly
language
syntax.
The
following
notation
is
used
to
describe
the
68000's
instruction
set.
Dn,
(An)
An
Data
and
address
register
direct.
Address
register
indirect.
Address
register
indirect
with
post-incrementing
or
pre-
decrementing.
Address
register
indirect
with
displacement,
and
address
register
indirect
with
indexing
and
a
displacement.
Absolute
addressing
with
a
16-bit
or
a
32-bit
address.
(An)+,
-(An)
(d,An),
(d,An,Xi)
ABS.W,
ABS.L
(d,PC),
(d,PC,Xi)
Program counter
relative
addressing
with
a
16-bit
offset,
or
with
an
8-bit
offset
plus
the
contents
of
an
index
register.
An
immediate
value
(i.e.,
literal)
which
may
be
16
or
32
bits,
depending
on
the
instruction.
i
mm
I
2
The
68000's
Instruction
Set
Two
notations
are
employed
for
address
register
indirect
addressing.
The
notation
originally
used
to
indicate
address
register
indirect
addressing
has
been
superseded.
However,
the
Teesside
68000
simulator
supports
only
the
older
form.
Old
notation
Current
notation
d(An),
d(An,Xi)
d(PC),
d(PC,Xi)
(d,An),
(d,An,Xi)
(d,PC),
(d,PC,Xi)
ABCD
Operation:
Syntax:
Add
decimal
with
extend
[destination]10
[source]10
+
[destination]10
+
[X]
ABCD
Dy,Dx
ABCD
-(Ay),-(Ax)
Size
=
byte
Add
the
source
operand
to
the
destination
operand
along
with
the
extend
bit,
and
store
the
result
in
the
destination
location.
The
addition
is
performed
using
BCD
arithmetic.
The
only
legal
addressing
modes
are
data
register
direct
and
memory
to
memory
with
address
register
indirect
using
pre-decrementing.
The
ABCD
instruction
is
used
in
chain
arithmetic
to
add
together
strings
of
BCD
digits.
Consider
the
addition
of
two
nine-digit
numbers.
Note
that
the
strings
are
stored
so
that
the
least-
significant
digit
is
at
the
high
address.
Attributes:
Description:
Application:
LOOP
LEA
LEA
MOVE
MOVE
ABCD
DBRA
N
U
Number1,A0
Number2,A1
#8,D0
#$04,CCR
-(A0),-(A1)
D0,LOOP
A0
points
at
first
string
A1
points
at
second
string
Nine
digits
to
add
Clear
X-bit
and
Z-bit
of
the
CCR
Add
a
pair
of
digits
Repeat
until
9
digits
added
Condition
codes:
X
*
Z
*
V
u
C
*
The
Z-bit
is
cleared
if
the
result
is
non-zero,
and
left
unchanged
otherwise.
The
Z-bit
is
normally
set
by
the
programmer
before
the
BCD
operation,
and
can
be
used
to
test
for
zero
after
a
chain
of
multiple-precision
operations.
The
C-bit
is
set
if
a
decimal
carry
is
generated.
The
68000's
Instruction
Set
3
ADD
Operation:
Syntax:
Add
binary
[destination]
ADD
<ea>,Dn
ADD
Dn,<ea>
Size
=
byte,
word,
longword
Add
the
source
operand
to
the
destination
operand
and
store
the
result
in
the
destination
location.
[source]
+
[destination]
Attributes:
Description:
Condition
codes:
X
N
Z
V
C
Source
operand
addressing
modes
Dn
✓
An
(An)
(An)+
-(An)
(d,An)
(d,An,Xi)
ABS.W
ABS.L
(d,PC)
(d,PC,Xn)
imro
✓
✓
✓
✓
Destination
operand
addressing modes
Dn
An
(An)
✓
(An)+
-(An)
(d.An)
(d,An,Xi)
ABS.W
ABS.L
(d,PC)
(d,PC,Xn)
imro
✓
✓
✓
ADDA
Operation:
Add
address
[destination]
ADDA
<ea>,An
Size
=
word,
longword
Add
the
source
operand
to
the
destination
address
register
and
store
the
result
in
the
destination
address
register.
The
source
is
sign-extended
before
it
is
added
to
the
destination.
For
example,
if
we
execute
ADDA.W
D3,A4
where
A4
=
00000100.
and
D3.W
=
16
800216,
the
contents
of
D3
are
sign-extended
to
FFFF800216
and
added
to
0000010016
to
give
FFFF810216,
which
is
stored
in
A4.
[source]
+
[destination]
Syntax:
Attributes:
Description:
4
The
68000's
Instruction
Set
Application:
To
add
to
the
contents
of
an
address
register
and
not
update
the
CCR.
Note
that
ADDA.W
D0,A0
is
the
same
as
LEA
(A0,D0.W),A0
.
Condition
codes:
X
N
Z
V
C
An
ADDA
operation
does
not
affect
the
state
of
the
CCR.
Source
operand
addressing
modes
Dn
✓
An
(An)
(An)+
-(An)
(d,An)
(d,An,Xi)
ABS.W
ABS.L
(d,PC)
(d,PC,Xn)
imro
✓
✓
✓
✓
ADDI
Operation:
Syntax:
Add
immediate
[destination]
ADDI
<iiterai>
+
[destination]
#<data>,<ea>
Attributes:
Description:
Size
=
byte,
word,
longword
Add
immediate
data
to
the
destination
operand.
Store
the
result
in
the
destination
operand.
ADDI
can
be
used
to
add
a
literal
directly
to
a
memory
location.
For
example,
ADDI.W
#$1234,$2000
has
the
effect
[M(200016)]
[M(200016)]
+
1234
16
.
Condition
codes:
X
N
Z
V
C
Destination
operand
addressing modes
Dn
An
(An)
✓
(An)+
-(An)
(d.An)
(d,An,Xi)
ABS.W
ABS.L
(d,PC)
(d,PC,Xn)
imro
✓
✓
✓
ADDQ
Operation:
Add
quick
[destination]
<literal>
+
[destination]
Syntax:
ADDQ
#<data>,<ea>
The
68000's
Instruction
Set
5
Sample
syntax:
ADDQ
#6,D3
Size
=
byte,
word,
longword
Add
the
immediate
data
to
the
contents
of
the
destination
operand.
The
immediate
data
must
be
in
the
range
1
to
8.
Word
and
longword
operations
on
address
registers
do
not
affect
condition
codes.
Note
that
a
word operation
on
an
address
register
affects
all
bits
of
the
register.
Attributes:
Description:
Application:
ADDQ
is
used
to
add
a
small
constant
to
the
operand
at
the
effective
address.
Some
assemblers
permit
you
to
write
ADD
and
then
choose
ADDQ
automatically
if
the
constant
is
in
the
range
1
to
8.
Condition
codes:
Z
N
Z
V
C
Note
that
the
CCR
is
not
updated
if
the
destination
operand
is
an
address
register.
Destination
operand
addressing modes
Dn
✓
An
✓
(Au)
✓
(An)+
-(An)
✓
✓
(d,An)
(d,An,Xi)
AB5.W
ABS.L
(d,PQ
(d,PC,Xn)
imm
✓
✓
✓
✓
ADDX
Operation:
Syntax:
Add
extended
[destination]
ADDX
Dy,Dx
ADDX
-(Ay),-(Ax)
Size
=
byte,
word,
longword
Add
the
source
operand
to
the
destination
operand
along
with
the
extend
bit,
and
store
the
result
in
the
destination
location.
The
only
legal
addressing
modes
are
data
register
direct
and
memory
to
memory
with
address
register
indirect
using
pre-
decrementing.
The
ADDX
instruction
is
used
in
chain
arithmetic
to
add
together
strings
of
bytes
(words
or
longwords).
Consider
the
addition
of
[source]
+
[destination]
+
[X]
Attributes:
Description:
Application:

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