SystemVerilog Interface.pdf

(1591 KB) Pobierz

SystemVerilog Interfaces

Gi-Yong Song

Chungbuk National University, Korea

SystemVerilog

SystemVerilog extends the Verilog language with a

powerful interface construct. Interfaces offer a new

paradigm for modeling abstraction. The use of

interfaces can simplify the task of modeling and

verifying large, complex designs.

Interface concepts

The Verilog language connects modules together

through module ports. This is a detailed method of

representing the connections between blocks of a

design that maps directly to the physical

connections that will be in the actual hardware.

For large designs, however, using module ports to

connect blocks of a design together can become

tedious and redundant