LNBP20.PDF

(531 KB) Pobierz
LNBP10 SERIES
LNBP20
LNBP SUPPLY AND CONTROL VOLTAGE
REGULATOR (PARALLEL INTERFACE)
s
s
s
s
s
s
s
s
s
s
s
COMPLETE INTERFACE FOR TWO LNBs
REMOTE SUPPLY AND CONTROL
LNB SELECTION AND STAND-BY
FUNCTION
BUILT-IN TONE OSCILLATOR FACTORY
TRIMMED AT 22KHz
FAST OSCILLATOR START-UP FACILITATES
DiSEqC ENCODING
TWO SUPPLY INPUTS FOR LOWEST
DISSIPATION
BYPASS FUNCTION FOR SLAVE
OPERATION
LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
AUXILIARY MODULATION INPUT EXTENDS
FLEXIBILITY
CABLE LENGTH COMPENSATION
INTERNAL OVER TEMPERATURE
PROTECTION
BACKWARD CURRENT PROTECTION
Multiwatt-15
December 2004
™
DESCRIPTION
Intended for analog and digital satellite receivers,
the LNBP is a monolithic linear voltage regulator,
assembled in Multiwatt-15, PowerSO-20 and
PowerSO-10, specifically designed to provide the
powering voltages and the interfacing signals to
the LNB downconverter situated in the antenna
via the coaxial cable. Since most satellite
receivers have two antenna ports, the output
voltage of the regulator is available at one of two
logic-selectable output pins (LNBA, LNBB). When
the IC is powered and put in Stand-by (EN pin
LOW), both regulator outputs are disabled to allow
the antenna downconverters to be supplied/
controlled by others satellite receivers sharing the
same coaxial lines. In this occurrence the device
will limit at 3 mA (max) the backward current that
could flow from LNBA and LNBB output pins to
GND.
For slave operation in single dish, dual receiver
systems, the bypass function is implemented by
an electronic switch between the Master Input pin
(MI) and the LNBA pin, thus leaving all LNB
powering and control functions to the Master
Receiver. This electronic switch is closed when
the device is powered and EN pin is LOW.
™
10
1
Power SO-20
PowerSO-10
The regulator outputs can be logic controlled to be
13 or 18 V (typ.) by mean of the VSEL pin for
remote controlling of LNBs. Additionally, it is
possible to increment by 1V (typ.) the selected
voltage value to compensate the excess voltage
drop along the coaxial cable (LLC pin HIGH).
In order to reduce the power dissipation of the
device when the lowest output voltage is selected,
the regulator has two Supply Input pins V
CC1
and
V
CC2
. They must be powered respectively at 16V
(min) and 23V (min), and an internal switch
automatically will select the suitable supply pin
according to the selected output voltage. If
adequate heatsink is provided and higher power
losses are acceptable, both supply pins can be
powered by the same 23V source without
affecting any other circuit performance.
The ENT (Tone Enable) pin activates the internal
oscillator so that the DC output is modulated by a
±0.3 V, 22KHz (typ.) square wave. This internal
oscillator is factory trimmed within a tolerance of
±2KHz, thus no further adjustments neither
external components are required.
A burst coding of the 22KHz tone can be
accomplished thanks to the fast response of the
ENT input and the prompt oscillator start-up. This
helps designers who want to implement the
DiSEqC protocols (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation
Rev. 8
1/21
LNBP10 SERIES - LNBP20
input pin is available (EXTM). An appropriate DC
blocking capacitor must be used to couple the
modulating signal source to the EXTM pin. When
external modulation is not used, the relevant pin
can be left open.
Two pins are dedicated to the overcurrent
protection/monitoring: CEXT and OLF. The
overcurrent protection circuit works dynamically:
as soon as an overload is detected in either LNB
output, the output is shut-down for a time t
off
determined by the capacitor connected between
CEXT and GND. Simultaneously the OLF pin, that
is an open collector diagnostic output flag, from
HIGH IMPEDANCE state goes LOW.
After the time has elapsed, the output is resumed
for a time t
on
=1/15t
off
(typ.) and OLF goes in HIGH
IMPEDANCE. If the overload is still present, the
protection circuit will cycle again through t
off
and
ton until the overload is removed. Typical t
on
+t
off
value is 1200ms when a 4.7µF external capacitor
is used.
This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still
ensuring excellent power-on start up even with
highly capacitive loads on LNB outputs.
The device is packaged in Multiwatt15 for
thru-holes mounting and in PowerSO-20 for
surface mounting. When a limited functionality in a
smaller package matches design needs, a range
of cost-effective PowerSO-10 solutions is also
offered. All versions have built-in thermal
protection against overheating damage.
Table 1: Ordering Codes
TYPE
LNBP10
LNBP11
LNBP12
LNBP13
LNBP14
LNBP15
LNBP16
LNBP20
(*) Available on request
Multiwatt-15
PowerSO-20
PowerSO-10
LNBP10SP-TR (*)
LNBP11SP-TR (*)
LNBP12SP-TR (*)
LNBP13SP-TR (*)
LNBP14SP-TR (*)
LNBP15SP-TR (*)
LNBP16SP-TR (*)
LNBP20CR
LNBP20PD-TR
Figure 1: Pin Configuration
(top view)
Multiwatt-15
PowerSo-20
PowerSO-10
2/21
™
™
(*): External components are needed to comply to level 2.x and above (bidirectional) DiSEqC
trademark or EUTELSAT.
bus hardware requirements. DiSEqC
is a
LNBP10 SERIES - LNBP20
Table 2: Pin Description
PIN NUMBER vs SALES TYPE (LNBP)
SYMBOL
V
CC1
NAME
FUNCTION
20CR 20PD 10SP 11SP 12SP 13SP 14SP 15SP 16SP
Supply Input 1 15V to 25V supply. It is
automatically selected
when V
OUT
= 13 or 14V
Supply Input 2 22V to 25V supply. It is
automatically selected
when V
OUT
= 18 or 19V
Output Port
See truth table voltage
and port selection. In
stand-by mode this port
is powered by the MI pin
via the internal Bypass
Switch
Logic control input: see
truth table
1
2
1
1
1
1
1
1
V
CC2
2
3
2
2
2
2
2
2
2
LNBA
3
4
3
3
3
3
3
3
3
V
SEL
EN
OSEL
GND
Output Volt-
age Selec-
tion:13 or 18V
(typ)
Port Enable Logic control input: see
truth table
Port Selection Logic control input: see
truth table
Ground
Circuit Ground. It is
internally connected to
the die frame
22KHz Tone
Enable
External
Capacitor
4
5
4
4
4
4
4
4
4
5
7
8
6
7
1
10
11
20
13
14
5
9
6
5
NA
6
5
NA
6
5
NA
6
5
NA
6
5
NA
6
5
NA
6
ENT
CEXT
EXTM
LLC
OLF
MI
LNBB
Logic control input: see
truth table
Timing Capacitor used
by the Dynamic
Overload protection.
Typical application is
4.7µF for a 1200ms
cycle
External Mod- External Modulation
ulator
Input. Needs DC
decoupling to the AC
source. if not used, can
be left open.
Line Length Logic control input: see
Compens.
truth table
(1V typ)
Over Load
Logic output (open
Flag
collector). Normally in
HIGH IMPEDANCE,
goes LOW when current
or thermal overload
occurs
Master Input In stand-by mode, the
voltage on MI is routed
to LNBA pin. Can be left
open if bypass function
is not needed
Output Port See truth tables for
voltage and port selection
9
10
7
8
7
8
7
8
7
8
7
8
7
8
7
8
11
15
NA
NA
NA
9
NA
9
9
12
16
NA
NA
9
NA
9
NA
10
13
17
NA
9
NA
NA
10
10
NA
14
18
NA
10
10
10
NA
NA
NA
15
19
10
NA
NA
NA
NA
NA
NA
NOTE: the limited pin availability of the PowerSO-10 package leads to drop some functions.
3/21
LNBP10 SERIES - LNBP20
Table 3: Absolute Maximum Ratings
Symbol
V
I
I
O
V
I
I
SW
P
D
T
stg
T
op
Parameter
DC Input Voltage (V
CC1
, V
CC2
, MI)
Output Current (LNBA, LNBB)
Logic Input Voltage (ENT, EN OSEL, VSEL, LLC)
Bypass Switch Current
Power Dissipation at T
case
< 85°C
Storage Temperature Range
Operating Junction Temperature Range
Value
28
Internally Limited
-0.5 to 7
900
14
-40 to +150
-40 to +125
Unit
V
mA
V
mA
W
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Table 4: Thermal Data
Symbol
R
thj-case
Parameter
Thermal Resistance Junction-case
Value
2
Unit
°C/W
Table 5: Logic Controls Truth Table
CONTROL I/O
OUT
IN
IN
IN
IN
IN
EN
L
H
H
H
H
H
H
H
H
OSEL
X
L
L
L
L
H
H
H
H
VSEL
X
L
H
L
H
L
H
L
H
PIN NAME
OLF
ENT
EN
OSEL
VSEL
LLC
LLCO
X
L
L
H
H
L
L
H
H
L
I
OUT
> I
OMAX
or T
j
> 150°C
22KHz tone OFF
See Table Below
See Table Below
See Table Below
See Table Below
V
LNBA
V
MI
- 0.4V (typ.)
13V (typ.)
18V (typ.)
14V (typ.)
19V (typ.)
Disabled
Disabled
Disabled
Disabled
H
I
OUT
< I
OMAX
22KHz tone ON
See Table Below
See Table Below
See Table Below
See Table Below
V
LNBB
Disabled
Disabled
Disabled
Disabled
Disabled
13V (typ.)
18V (typ.)
14V (typ.)
19V (typ.)
NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ)
4/21
LNBP10 SERIES - LNBP20
Figure 2: Block Diagram
5/21

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin