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E
Additional Flash Data
Protection Using VPP,
RP#, and WP#
AP-617
APPLICATION
NOTE
December 1998
Order Number: 292172-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-879-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION1995, 1996, 1997, 1998
CG-041493
*Third-party brands and names are the property of their respective owners.
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AP-617
CONTENTS
PAGE
PAGE
FIGURES
Figure 1. Various Levels of Protection May Be
Added to Flash .................................14
Figure 2. When V
PP
Resides below V
PPLK
Program and Erase Commands to the
Flash Device Are Prevented ...............6
Figure 3. This SmartVoltage Circuit Will
Prevent Program and Erases When
Lockall# Is Asserted ...........................7
Figure 4. This Circuit Offers Reliable Lockall#
Protection in a 12 V V
PP
System.........8
Figure 5. Although This Circuit Will Cost Less
to Implement, It Requires More
Current Than Other Solutions .............8
Figure 6. Implementing Unlock# and Reset#
Inputs Using a Jumper Reduces Cost,
but Also Decreases Convenience .....10
Figure 7. If a Microcontroller Attempts to Fetch
Code before Memory Resets, a Delay
Circuit Such As This One Should Be
Added ...............................................10
Figure 8. The 28F200B5-T Divides Memory into
Asymmetrical Blocks and Allows the
Boot Block to Be Locked...................12
Figure 9. Example Advanced/Advanced+ Boot
Block Memory Top Configuration......14
Figure 10. The 28F008S3 Has Sixteen
Separately Eraseable Blocks ............15
TABLES
Table 1. Control Circuit Index by Flash Density .5
Table 2. Advantages of Each V
PP
Circuit ..........6
Table 3. 5 V/12 V V
PP
Lockall# Circuit Truth
Table ...................................................7
Table 4. Write Protection Truth Table for the
5 Volt Boot Block Family ......................9
Table 5. Write Protection Truth Table for the
Advanced/Advanced+ Boot Block
Flash Memory Family ..........................9
Table 6. Reset# and Unlock# Circuit Truth
Table ...................................................9
Table 7. Reset to First Data Latch ...................15
1.0 INTRODUCTION .............................................5
2.0 FLASH DATA PROTECTION AND
EXTERNAL CONTROL MECHANISMS.........5
3.0 VPP CHARACTERISTICS...............................6
3.1 V
PP
Solution: Implementing a Lockall#
Input............................................................7
3.1.1 5 V/12 V Lockall# DC-DC Converter
Solution ................................................7
3.1.2 5 V Lockall# Mosfet Solution .................7
3.1.3 12 V Lockall# Mosfet Solution ...............7
3.1.4 12 V Lockall# Mosfet with Resistor
Solution ................................................7
4.0 P-CHANNEL ENHANCEMENT MODE
MOSFET SELECTION ...................................8
5.0 RP# AND WP# CHARACTERISTICS..............8
5.1 RP# and WP# Solutions: Implementing a
Reset# and Unlock# Input ...........................9
5.1.1 RP# Jumper Solution.............................9
6.0 INTEL
®
MICROCONTROLLER AND
MICROPROCESSOR RESET TIMING
CONSIDERATIONS .....................................10
6.1 CPU Reset and RP# Timing.......................10
6.2 CPU Reset Delay Techniques....................10
7.0 SUMMARY ....................................................11
APPENDIX A: Boot Block and FlashFile™
Memory Architecture ..................................12
APPENDIX B: Reset Considerations ................15
APPENDIX C: Potential Sources for P-Channel
Mosfet Devices............................................17
APPENDIX D: Additional Information ...............18
3
AP-617
E
REVISION HISTORY
Description
Original Version
Added data protection information for Advanced/Advanced+ Boot Block products and
3 Volt and 5 Volt FlashFile memory products.
Removed information relating to discontinued products.
Minor text edits.
Number
-001
-002
4
E
1.0
INTRODUCTION
2.0
The introduction of reprogrammable, nonvolatile
memory necessitates measures to protect stored
information. Intel
®
Flash memory offers many advanced
features to protect data integrity. Internal circuitry can
help protect data at power-up, preventing spurious
writes caused by power or signal glitches. Control pins,
such as Reset Power-Down (RP#), Write Protect (WP#),
Chip Enable (CE#), and Write Enable (WE#) inherently
protect data integrity and control data flow. In today’s
diverse applications, system designers may desire to add
optional circuitry to exploit these features. For example,
general purpose I/O lines can be used to control write
capability to the flash device.
This application note will first examine the functions of
V
PP
, RP#, and WP# for the boot block devices. Other
devices, such as the 28F016 Intel
®
FlashFile™ memory,
offer similar features. Several optional system-level
circuit solutions which utilize V
PP
and RP# to increase
write control will then be discussed. Finally,
microcontroller reset timings will be addressed. A brief
discussion of boot block and FlashFile memory
architectures is included in Appendix A. Table 1
provides an index of the write protection options
available to each Intel Flash memory component.
Table 1. Control Circuit Index by Flash Density
Density
28F010, 28F020
28F001BX,
28F002BC
28F200B5,
28F400/004B5,
28F800B5
28F008SA
28F004S3/S5,
28F008S3/S5,
28F016S3/S5,
28F160S3/S5,
28F320S3/S5
28F400B3,
28F800/008B3,
28F160/016B3,
28F320/032B3
28F800/008C3,
28F160/016C3,
28F320/032C3
Available Options
V
PP
V
PP
, RP#
V
PP
, RP#, WP#
Section
3.1
3.1, 5.1
3.1, 5.1
Inherent
Protection
AP-617
FLASH DATA PROTECTION AND
EXTERNAL CONTROL
MECHANISMS
Intel Flash provides several mechanisms to prevent
unintentional writes. This protection is built into, and
inherent to, the functions of V
PP
, V
CC
, RP#, WP#, and
CE#. The same circuits that prevent unintentional writes
make these signals well-suited for optional control
circuits. In the following sections, the functions of V
PP
,
RP#, and WP# will be examined along with circuits
which use these signals for greater write control.
Many systems do not need additional protection since
Intel Flash inherently provides a level of protection.
However, in some circumstances additional protection
might be considered necessary. Unlike other types of
memory, flash retains data after power has been
removed. Thus, any inadvertent writes to flash are
retained. Alternatively, a write to flash could place the
device into a mode other than read, thus potentially
preventing the system from booting properly. Flash is
most vulnerable in three main circumstances:
•
•
•
Unstable control signals during power-up and
power-down
During the execution of runaway code
Control signal
operation
glitches
during
steady-state
Figure 1 shows the various levels of write protection
available for use in designs.
V
PP
, RP#
V
PP
, RP#, and
Software
3.1, 5.1
3.1
RP#, WP# Boot
Block Protection
V
PP
, RP#, WP#
3.1
V
PP
Held below V
PPLK
RP# Holding Chip in Reset
V
PP
, RP#, WP#,
and Software
3.1
Jumper or Physical Connection
2172_01
Figure 1. Various Levels of Protection May Be
Added to Flash
5

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