29F010.pdf

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FINAL
Am29F010
1 Megabit (131,072 x 8-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
s
Compatible with JEDEC-standards
— Pinout and software compatible with
single-power-supply Flash
— Superior inadvertent write protection
s
32-pin PLCC
32-pin TSOP
32-pin PDIP
s
Minimum 100,000 write/erase cycles
guaranteed
s
High performance
— 45 ns maximum access time
s
Sector erase architecture
— Uniform sectors of 16 Kbytes each
— Any combination of sectors can be erased.
Also supports full chip erase
s
Sector protection
— Hardware method that disables any combina-
tion of sector(s) from write or erase operations
s
Embedded Erase
TM
Algorithms
Advanced
Micro
Devices
— Automatically pre-programs and erases the
chip or any sector
s
Embedded Program
TM
Algorithms
— Automatically programs and verifies data at
specified address
s
Data
Polling and Toggle Bit feature for
detection of program or erase cycle
completion
s
Low power consumption
— 30 mA maximum active read current
— 50 mA maximum program/erase current
s
Enhanced power management for standby
mode
— <25
µA
typical standby current
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 128 Kbytes of 8 bits each. The 1 Mbit of
data is divided into 8 sectors of 16 Kbytes for flexible
erase capability. The 8 bits of data will appear on
DQ0–DQ7. The Am29F010 is offered in 32-pin
packages which allows for upgrades to 4 Mbit densities
in the same pin out. This device is designed to be
programmed in-system with the standard system
5.0 Volt VCC supply. 12.0 Volt VPP is not required for pro-
gram or erase operations. The device can also be
reprogrammed in standard EPROM programmers.
The standard Am29F010 offers access times between
45 ns and 120 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F010 is entirely command set compatible with
the JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from 12.0 Volt
Flash or EPROM devices.
The Am29F010 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This will in-
voke the Embedded Erase Algorithm which is an inter-
nal algorithm that automatically preprograms the array if
it is not already programmed before executing the erase
operation. During erase, the device automatically times
the erase pulse widths and verifies proper cell margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and
reprogrammed without affecting the data contents of
other sectors. A sector is typically erased and verified
within one second. The Am29F010 is erased when
shipped from the factory.
Publication#
16736
Rev.
F
Amendment
/0
Issue Date:
November 1995
1-3
AMD
GENERAL DESCRIPTION (continued)
The Am29F010 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of eight sectors
of memory.
The device features single 5.0 Volt power supply opera-
tion for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations. A low VCC detector auto-
matically inhibits write operations during power transi-
tions. The end of program or erase is detected by the
Data
Polling of DQ7 or by the Toggle Bit (DQ6). Once
the end of a program or erase cycle has been
completed, the device automatically resets to
the read mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F010 memory electrically erases all
bits within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
Flexible Sector-Erase Architecture
s
Eight 16 Kbyte sectors
s
Individual-sector or multiple-sector erase capability
s
Sector protection is user definable
16 KByte
16 KByte
16 KByte
16 KByte
16 KByte
16 KByte
16 KByte
16 KByte
1FFFFh
1BFFFh
17FFFh
13FFFh
0FFFFh
0BFFFh
07FFFh
03FFFh
00000h
16736F-2
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
1-4
Am29F010
AMD
PRODUCT SELECTOR GUIDE
Family Part No:
Ordering Part No:
V
CC
= 5.0 Volt
±
5%
V
CC
= 5.0 Volt
±
10%
Max Access Time (ns)
CE
(E) Access (ns)
OE
(G) Access (ns)
Am29F010
-45
-55
45
45
25
55
55
30
-70
70
70
30
-90
90
90
35
-120
120
120
50
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
Erase Voltage
Switch
Input/Output
Buffers
WE
State
Control
Command
Register
PGM Voltage
Switch
Chip Enable
Output Enable
Logic
Data
Latch
CE
OE
Embedded
Algorithms
V
CC
Detector
Timer
A
d
d
r
e
s
s
L
a
t
c
h
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A16
16736F-1
Am29F010
1-5
AMD
CONNECTION DIAGRAMS
PDIP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
(W)
NC
A14
A13
A8
A9
A11
OE
(G)
A10
CE
(E)
DQ7
DQ6
DQ5
DQ4
DQ3
16736F-3
PLCC
WE
(W)
NC
A16
4 3 2
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
1 32 31 30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
(G)
A10
CE
(E)
DQ7
14 15 16 17 18 19 20
V
SS
DQ3
DQ1
DQ2
DQ4
DQ5
DQ6
V
CC
A12
A15
NC
16736F-4
TSOP
A11
A9
A8
A13
A14
NC
WE
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
16736F-5
29F010 Standard Pinout
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
V
CC
NC
A16
A15
A12
A7
A6
A5
A4
29F010 Reverse Pinout
1-6
Am29F010
16736F-6
AMD
PIN CONFIGURATION
A0–A16
CE
DQ0–DQ7
NC
OE
V
CC
=
=
=
=
=
17 Addresses
Chip Enable
LOGIC SYMBOL
= 8 Data Inputs/Outputs
Pin Not Connected Internally
Output Enable
+5.0 Volt Single-Power Supply
(±10% for –55, –70, –90, –120) or
(±5% for –45)
Device Ground
Write Enable
17
A0 – A16
8
DQ0 – DQ7
CE
(E)
OE
(G)
WE
(W)
V
SS
WE
=
=
16736F-7
Am29F010
1-7

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