MC68030_Data_Sheet_1991.pdf

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MOTOROLA
by MC68030/D
-
TECHNICAL DATA
SEMICONDUCTOR
MC68030
Technical Summary
Second-Generation 32-Bit
..
Enhanced Microprocessor
The MC68030 is a 32-bit virtual memory microprocessor that integrates the
functionality of an MC68020 core with the added capabilities of an on-chip
paged memory management unit (MMU) and an on-chip 256-byte data cache.
Additionally, the MC68030 is enhanced with multiple internal address and data
buses as well as a more versatile bus controller that can support two-clock bus
accesses and one-clock burst accesses to maximize performance. The rich in-
struction set and addressing mode capabilities of the MC68020 have been
maintained, allowing a clear migration path for M68000 systems. For detailed
information on the MC68030, refer to MC68030UM/AD,
MC68030 Enhanced
32-Bit Microprocessor User's Manual.
The main features of the MC68030 are as follows:
• Object-Code Compatible with the MC68020 and Earlier M68000 Micropro-
cessors
• Complete 32-Bit Nonmultiplexed Address and Data Buses
• 16 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and 10 Special-Purpose Control Reg-
isters
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed
Simultaneously
• Paged MMU Translates Addresses in Parallel with Instruction Execution
• Two Transparent Segments Allow Untranslated Blocks To Be Defined for
Systems That Transfer Large Blocks of Data to Predefined Addresses -
i.e., Graphics Applications
• Pipelined Architecture with Increased Parallelism Allows Accesses from
Internal Caches to Occur in Parallel with Bus Transfers and Instruction
Execution To Be Overlapped
This document contains information on a new product. Specifications and information hert::m are SUDJeCI IO cnange Wltnout notice.
MOTOROLA _
©MOTOROLA INC., 1991
Rev. 3
• Enhanced Bus Controller Supports Asynchronous Bus Cycles, (three clocks
minimum), Synchronous Bus Cycles, (two clocks minimum), and Burst
Data Transfers (one cock minumum), all to the Physical Address Space
• Dynamic Bus Sizing Supports 8-/16-/32-Bit Memories and Peripherals
• Complete Support for Coprocessors with the M68000 Coprocessor Inter-
face
• Internal Status Indication for Hardware Emulation Support
• 4-Gbyte Direct Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and
HMOS (High-Density NMOS) Gates To Be Combined for Maximum Speed,
Low Power, and Small Die Size
• Processor Speeds Beyond 20 MHz
INTRODUCTION
The MC68030 is an integrated processor that incorporates the capabilities of
the MC68020 microprocessor, the memory management structure defined by
the MC68851 paged memory management unit (PMMU), data cache, an in-
struction cache, and an improved bus controller on one VLSI device. It maintains
the 32-bit registers available with the entire M68000 Family as well as the
32-bit address and data paths, rich instruction set, versatile addressing modes,
and flexible coprocessor interface provided with the MC68020. In addition, the
internal operations of this integrated processor are designed to operate in
parallel, allowing multiple instructions to be executed concurrently. It allows
instruction execution to proceed in parallel with accesses to the internal caches,
the on-chip MMU, and the bus controller.
The MC68030 fully supports the nonmultiplexed asynchronous bus of the
MC68020 as well as the dynamic bus sizing mechanism that allows the pro-
cessor to transfer operands to or from external devices while automatically
determining device port size on a cycle-by-cycle basis. In addition to the asyn-
chronous bus, the MC68030 also supports a fast synchronous bus for off-chip
caches and fast memories. Furthermore, the MC68030 bus is capable offetching
up to four long words of data in a burst mode compatible with DRAM chips
that have burst capability. Burst mode can reduce (up to 50 percent) the time
necessary to fetch the four long words. The four long words are used to prefill
the on-chip instruction and data caches so that the hit ratio of the caches is
improved and the average access time for operand fetches is minimized.
2
MC68030 TECHNICAL DATA
MOTOROLA
The block diagram shown in Figure 1 depicts the major sections of the MC68030
and illustrates the autonomous nature of these blocks. The bus controller con-
sists of the address and data pads, the multiplexers required to support dynamic
bus sizing, and a microbus controller that schedules the bus cycles on the basis
of priority. The micromachine contains the execution unit and all related control
logic. Microcode control is provided by a modified two-level store of microROM
and nanoROM contained in the micromachine. Programmed logic arrays (PLAs)
are used to provide instruction decode and sequencing information. The in-
struction pipe and other individual control sections provide the secondary de-
code of instructions and generate the actual control signals that result in the
decoding and interpretation of nanoROM and microROM information.
The instruction and data cache blocks operate independently from the rest of
the machine, storing information read by the bus controller for future use with
very fast access time. Each cache resides on its own address bus and data bus,
allowing simultaneous access to both. Both caches are organized as a total of
64 long-word entries (256 bytes) with a line size of four long words. The data
cache uses a write-through policy with programmable write allocation for cache
misses.
Finally, the MMU controls the mapping of addresses for page sizes ranging
from 256 bytes to 32K bytes. Mapping information stored in descriptors resides
in translation tables in memory that are automatically searched by the MC68030
on demand. Recently used descriptors are maintained in a 22-entry fully as-
sociative cache called the address translation cache (ATC), allowing address
translation and other MC68030 functions to occur simultaneously. Additionally,
the MC68030 contains two transparent translation registers that can be used
to define a one-to-one mapping for two segments ranging in size from 16
Mbytes to 2 Gbytes each.
MOTOROLA
MC68030 TECHNICAL DATA
3
MICROSEQUENCER AND CONTROL
INTERNAL
DATA
BUS
INSTRUCTION
ADDRESS
BUS
(")
0)
EXECUTION UNIT
3:
co
c
w
c
(")
m
-I
ADDRESS
BUS
ADDRESS
PADS
SIZE
MULTIPLEXER
DATA
BUS
:::t:
~
r-
Z
;
l>
C
DATA
ADDRESS
BUS
o
-t
o
:0
o
~
s:
BUS CONTROL
SIGNALS
Figure 1. MC68030 Block Diagram
PROGRAMMING MODEL
As shown in the programming models (see Figures 2 and 3), the MC68030 has
16 32-bit general-purpose registers, a 32-bit program counter, two 32-bit super-
visor stack pointers, a 16-bit status register, a 32-bit vector base register, two
3-bit alternate function code registers, two 32-bit cache handling (address and
control) registers, two 64-bit root pointer registers used by the MMU, a 32-bit
translation control register, two 32-bit transparent translation registers, and a
16-bit MMU status register. Registers 00-07 are used as data registers for bit
and bit field (1 to 32 bit), byte (8 bit), word (16 bit), long-word (32 bit), and
quad-word (64 bit) operations. Registers AO-A6 and the user, interrupt, and
master stack pointers are address registers that may be used as software stack
pointers or base address registers. In addition, the address registers may be
used for word and long-word operations. All 16 general-purpose registers
(00-07, AO-A7) can used as index registers.
31
16 15
8 7
0
DO
01
02
03
04
05
06
07
31
16 15
0
DATA
REGISTERS
AO
A1
A2
A3
ADDRESS
REGISTERS
A4
A5
A6
I
31
.
I
I
I
I
I
tJsP}
0
USER STACK
POINTER
PROGRAM
COUNTER
CONDITION CODE
REGISTER
I
15
7
I
PC
0
C~~~~~O~~~~~~
I
I
CCR
Figure 2. User Programming Model
MOTOROLA
MC68030 TECHNICAL DATA
5

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