LA-8661P Compal QAU30 HP Envy Sleekbook 6.pdf

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Compal Confidential
Lotus M/B Schematics Document
14": Elise; 15.6" Exige
2
Intel Ivy Bridge ULV Processor with DDRIII + Panther Point
3
Date : 2011/10/27
Version 0.1
3
4
4
Security Classification
Issued Date
2011/06/29
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
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D
Block Diagrams
Size Document Number
Custom
Date:
LA-8551P
Sheet
E
Rev
0.1
1
of
55
Friday, March 02, 2012
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Compal Confidential
Model Name : Lotus
1
File Name : LA8661P
2011/11/01
128Mx16
AMD
128Bit
VRAMx8pcs
DDRIII
P28, P29
PEG 3.0 x16
(2 x8)
Intel
IVY Bridge
ULV Processor
FCBGA 1023
31mm*24mm
DDR3 1333/1600MHz 1.5V
DDR3L 1333MHz 1.35V
Dual Channel
1
DDR3-SO-DIMM X 2
BANK 0, 1, 2, 3
P12, P13
Thames-XT
25W
P22~ P29
P5~ P11
FDI x8
HDMI Conn.
DDPB port
P30
P32
DMI x4
100MHz
5GT/s
Daughter board
LVDS Conn.
LVDS(1Ch/2ch)
HDMI
PCI-Express x 8 (PCIE2.0 5GT/s)
SATAx2
100MHz
100MHz
X1
100MHz
2.7GT/s
USB3.0 x2
port1,3 port0,2 P35
USB2.0 x1
port1
USB charger
X1
2
2
Intel
Panther Point
PCH
989pin BGA
25mm*25mm
USB 3.0 x2
USB 2.0 x4
HD Audio
SPI
X2
3.3V 48MHz
X2
X1
3.3V 24MHz
port8
X1
X1
X1
HD webcam
D-MIC(daul)
(GEN1 1.5Gb/S
GEN2 3Gb/S
GEN3 6Gb/S)
port0
port1
P14~ P21
HDA Codec
LPC BUS
33MHz
Card Reader
/LAN controller
RTL8411
RJ45
P34
JMINI1
WLAN&BT
(mini card)
P31
X1
port1
JMINI2
m-SATA
(mini card)
P33
X1
port0
SATA HDD
P33
BIOS SPI ROM,
4MB +2 MB
P14
IDT 92HD91
P38
P34
port9
port5
SPK conn
USB 2.0 x2
P41
Sub Woofer
Amp
P39
Sub Woofer
conn
P39
HP Amp
P40
3
3
SD socket
Daughter board
Accelerometer
HP3DC2
P42
FAN conn.
P37
TPM1.2
SLB9635/9656
P42
HP&MIC
jack
S/B
Daughter board
ENE KB932
P36
Touch pad daughter board
LED
RTC CKT.
4
PS2
P37
P14
P37
SPI
Lid switch
S/B
Touch Pad
P37
Int.KBD
P37
EC ROM,
256kB
P36
FAN/LED
P37
4
Power On/Off CKT.
DC/DC interface CKT.
P43
SM_BUS
(PCH)
Security Classification
Issued Date
2011/06/29
Compal Secret Data
Deciphered Date
2011/06/29
Title
Compal Electronics, Inc.
Block Diagrams
Size Document Number
Custom
Date:
Rev
0.1
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
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C
D
LA-8551P
2
of
55
Friday, March 02, 2012
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QAU30/50 (LA-8661P Ver:0.1)
Voltage Rails
Power Plane
VIN
BATT+
B+
1
STATE
Full ON
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
+VS
ON
ON
OFF
OFF
OFF
Clock
ON
LOW
OFF
OFF
OFF
1
Description
Adapter power supply (19V)
Battery power supply (12.6V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for UMA graphic
+0.75VP to +0.75VS switched power rail for DDR terminator
+V1.05SP to +1.05VS_VCCP switched power rail for CPU
+VCCP (1.05V ) power for PCH
+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)
+1.5VS switched power rail
(+5VALW ) to 1.8V switched power rail to PCH
+3VALW always on power rail
+3VALW always to KBC
+3VALW to +LAN_IO power rail for LAN
+3VALW to +3V_PCH power rail for PCH (Short Jumper)
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5V_PCH power rail for PCH (Short resister)
+5VALW to +5VS switched power rail
B+ to +VSB always on power rail for sequence control
RTC power
S1
N/A
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
N/A
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
ON
ON
OFF
ON
ON
OFF
ON
ON
S5
N/A
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON*
ON*
ON*
ON*
OFF
ON*
ON*
OFF
ON*
ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
+CPU_CORE
+VGFX_CORE
+0.75VS
+1.05VS_VCCP
+VCCP
+1.5V
+1.5VS
+1.8VS
+3VALW
+3VALW_EC
+LAN_IO
+3V_PCH
+3VS
+5VALW
+5V_PCH
+5VS
+VSB
+RTCVCC
Power Plane
+VGA_CORE
+3VGS
+1.8VGS
+1.5VGS
+1.0VGS
Description
GPU power
GPU power
GPU power
GPU power
GPU power
S1
PX
PX
PX
PX
PX
S3
OFF
OFF
OFF
OFF
OFF
S5
OFF
OFF
OFF
OFF
OFF
EC SM Bus1 address
Device
Smart Battery
G-sensor
Address
0x50/0x52
EC SM Bus2 address
Device
PCH (Reserve)
2
Address
2
PCH SM Bus address
Device
DDR DIMM0
DDR DIMM1
Mini Card1
Mini Card2
TP module
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Address
CLKOUT DESTINATION
PCI0
PCI1
PCH_LPBACK
PCI_LPC
None
None
None
SMBUS Control Table
WLAN
MIINI1
BATT
Charger
EC_SMB_CK2
EC_SMB_DA2
PCH_SML1CLK
PCH_SML1DATA
SOURCE
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1CLK
PCH_SML1DATA
KB930
KB930
PCH
PCH
PCH
BATT
TP
SODIMM
G-Sensor
GPU
HP AMP
PCI2
PCI3
V
@
V
V
V
V
V
V
V
PCI4
USB Port Table
SATA
DESTINATION
USB 2.0 USB 1.1 Port
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2
UHCI5
UHCI6
Option
UMA
DIS
@
X
X
CONN@
X
X
USB30@
V
V
PX@
X
V
UMA@
V
X
DIS@
X
V
THA@
X
V
3
V
BY SKU
SATA0 SATA, JHDD1
SATA1 m-SATA,JMINI2
9656@
DIFFERENTIAL
CLKOUT_PCIE0
DESTINATION
PCIE LAN
CARD READER
mini WLAN
None
None
None
None
FLEX CLOCKS
CLKOUTFLEX0
CLKOUTFLEX1
DESTINATION
None
TPM
9635@
SATA2
SATA3
SATA4
SATA5
None
None
None
None
CPUUMA1@
CPU
CPUUMA2@
CPUDIS@
VRAM
X76@
M2G@
H2G@
S2G@
None
None
DGPU_PRSNT#
CLKOUT_PCIE1
CLKOUTFLEX2
CLKOUTFLEX3
CLK
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Port
1
2
3
3 External
USB Port
USB2.0 (left Side)
USB2.0 (right Side)
USB2.0 (left Side)
3
None
None
None
None
None
Camera
Mini Card(WLAN& BT)
None
None
None
None
2 External
USB Port
USB3.0 (left Side)
 
¡
¢
£
¤¥
¦
¤§
¨
©
4
!
"
#
$
%
USB 3.0
CLKOUT_PCIE5
CLKOUT_PCIE6
CLKOUT_PCIE7
CLKOUT_PEG_B
A
4
&
#
!
"
#
$
%
None
USB3.0 (left Side)
None
Project ID
30UMA@
30DIS@
50UMA@
50DIS@
Security Classification
4
Compal Secret Data
2011/06/29
Deciphered Date
2011/06/29
Title
None
Compal Electronics, Inc.
Notes List
None
None
B
PCB
LA-8661P
PX@
LA-8662P
UMA@
C
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
Size
C
Date:
Document Number
LA-8661P
Friday, March 02, 2012
E
Rev
0.1
3
of
55
Sheet
5
4
3
2
1
D
D
C
C
B
B
A
A
Security Classification
Issued Date
2011/06/29
Compal Secret Data
Deciphered Date
2011/06/29
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
PROCESSOR(1/7) DMI,FDI,PEG
Size
B
Date:
Document Number
Friday, March 02, 2012
Sheet
1
Rev
0.1
4
of
55
5
4
3
2
1
UCPU1
CPUDIS01@
i5-2467M CPU
SA00004X000
Sandy Bridge:
Intel Core i5-2467M: SA00004X000 (4619HY32L01)
UCPU1
CPUDIS02@
i5-2367M CPU
SA000051H20
UCPU1
CPUUMA3@
i5-2367M CPU
SA000051H20
D
UCPU1
CPUUMA1@
17W 1.5GHz GT2 ES2 QBP8
SA00005AZ10
Ivy Bridge:
1.5GHz GT2 ES2 QBP8: SA00005AZ10 (4619HZ32L01)
1.5GHz ES2 QBTP: SA00005AZ20(4619HZ32L02)
+VCCP
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
D
UCPU1
CPUDIS03@
i5-2367M CPU
SA000051H20
UCPU1
CPUDIS04@
i5-3317U CPU
SA00005K600
UCPU1
CPUUMA5@
17W 1.7GHz no cnfg ES2 QBTQ
SA00005B020
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
M2
P6
P1
P10
N3
P7
P3
P11
K1
M8
N4
R2
K3
M7
P4
T3
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G3
G1
G4
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG_COMP
2
UCPU1
CPUUMA4@
17W 1.7GHz GT2 ES2 QBP7
SA00005B010
UCPU1
CPUUMA2@
17W 1.5GHz no cnfg ES2 QBTP
SA00005AZ20
RC1
24.9_0402_1%
UCPU1A
@
1
1
CU65
0.1U_0402_16V4Z
2
Add CU65 0.1U as EMI request.
12.19
DMI
<PEG>
C
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
+VCCP
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
U6
W10
W3
AA7
W7
T4
AA3
AC8
AA11
AC12
U11
AA10
AG8
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
<16> FDI_FSYNC0
<16> FDI_FSYNC1
<16> FDI_INT
RC88
@
10K_0402_5%
RC2
24.9_0402_1%
<16> FDI_LSYNC0
<16> FDI_LSYNC1
B
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
PCI EXPRESS -- GRAPHICS
<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
U7
W11
W1
AA6
W6
V4
Y2
AC9
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
C
Intel(R) FDI
2
1
2
1
EDP_COMP
AF3
AD2
AG11
AG4
AF4
<PEG>
B
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX#
eDP_AUX
eDP
NOTE:eDP_COMPIO and eDP_ICOMPO
should not be left floating even if Internal
Graphic is disabled since they are shared
with other interfaces
AC3
AC4
AE11
AE7
AC1
AA4
AE10
AE6
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
IVY-BRIDGE_BGA1023
10/05 Change to 0.22uF.
Typ- suggest 220nF. The change in AC capacitor
value from 180nF to 265nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A
A
Security Classification
Issued Date
2011/06/29
Compal Secret Data
Deciphered Date
2011/06/29
Title
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
LA-8661P
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Size Document Number
Custom
Date:
Rev
0.1
5
of
58
Friday, March 02, 2012

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