One-More-Electronic-Keyer.pdf

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one more
electronic
keyer
During the past
few
years
several articles
have appeared describing the electronic
kev.1.":' Here's one more. Thiq key is a
TO
type and is basically the same as the one de-
~ r i b e d K3CUW in
QST.1
Its features are:
by
1.
2.
3.
4.
Adot memory
3
.
-
m
L
ensures positive
C
Y
3
character formation
in this improved
version of the
:
:
2
4
UJ
A
dot memory
Small size
Npn or Pnp transistor switching
"Squeeze-key" operation if desired.
0;
5
-
TO
keyer
-
I'll start by offering some motivation for its
design, followed by a review of the inte-
grated circuit (IC) characteristics.
I
first became familiar with electronic keys
with the construction of an all-transistor
TO
key,.' which I used extrnsivcly for about five
years. In constructing a new key,
I
felt I
s h o ~ ~strive for increased ease of operation
ld
and a
substantial
reduction i n size. (The key
mentioned above occupied 3'/zx6xR inches
on the operating table.)
For easier operation, an clccfronic key
must have a mrniory. Keys have been de-
scrilwd \vilh clot ancl rlash rnrmotiri;'.'; I ~ u It
decitlcd that a key with a do1 Inrmory \voulcl
only he hest for the reasons givrn I ~ c l o w .
If you now use an electrclnic kc), will1
no
32
november
1969
Main circuit
board.
of their operation. Rather than consider IC
operation in terms of Boolean functions, I'II
regard them as black boxes with particular
characteristics.
I
believe it's less confusing
to use this approach for a practical under-
standing of their operation.
The symbols and names are borrowed from
the language of Boolean algebra (for ex-
ample, the gate
i s
a
NOR
gate). But it's best
to understand the way in which the circuit
works rather than the logic functions in-
volved.
Let's first consider a gate. Its symbol, and
a table describing
i t s
operation, are as fol-
lows:
memory, you know that one of the most
common errors
is
the omission of a dot in
letters such as n, k, c, y, etc. This error can be
corrected if a dot memory
i s
included, which
will insert the dot if the paddle
is
closed dur-
ing the preceding dash.
Because it's longer, a dash followed by a
dot
is
seldom omitted. The natural tendency
to hold the paddle on the dash side for a
longer time ensures that the dash will be
formed.
A dash memory would be required if the
key had a free-running clock, a in the Ulti-
s
matic.b.6 However,
I
felt that a
gated
clock
would make the key easier to operate, be-
cause the response to touching the paddle
is
immediate. The free-running clock key
may delay up to a whole dot duration before
doing anything.
The small size requirement suggested,
(1)
integrated circuits and,
(2)
that something
be done about the huge filter capacitors or-
dinarily required for low-voltage, high-cur-
rent power supplies. An electronically regu-
lated supply takes care of the latter problem.
Note that
H
stands for a high-voltage level,
and L stands for a low-voltage level. For the
gate, the table shows a high level out for two
low levels in, but low level out otherwise.
A flip-flop
is
represented by this symbol
and truth table:
S
H
C
1
OUTPUT
NO
M N e E
n
L
review of ic operation
The IC's used in this keyer should be in
fairly common use by now.7 For complete-
ness, however, I'II include a brief description
n
L
n
L
COIRTWLNT
L
n
L
A
printed-circuit board for this keyer is available for
$3.00
from Stafford Electronics,
427
South Benbow
Road, Greensboro, North Carolina
27401;
order part
no.
HR
11-69A. A
kit of IC's, transistors and diodes
(less power supply) are available from the same source
for
$8.50.
A high level on the preset
(PS)
terminal
results in a low output at the
1
terminal.
Any other change of state of the flip-flop re-
quires a negative-going pulse on the toggle
(T) input. (This pulse must be
fast,
I
might
add-less than 100 ns for the IC's used in
this keyer.) The terminal-I output after a
toggle is shown in the table.
november 1969
33
With a low on
S
and
C,
the flip-flop
changes state (complements), and the out-
puts return to the same state as the inputs
after a toggle if there
i s
an H-L or 1-H com-
bination on the inputs.
Now these are the only two different types
of IC's used in the keyer, but three simple
gate connections are described so a block
diagram can be drawn. First, a monostable,
or one-shot:
The second connection is a set-reset R-S
flip-flop:
8
. - -.-
-- .--
-.
-
- -
.--
-J
5
R
"1.
OUTPUT
consider the following input signal:
Before t, occurs, the capacitor is charged
to V
=
Vcc
-
RI, where
I
is the current flow-
ing into the gate, Vc,I(R
450). (The gate
input resistance is 450 ohms.) The gate has
an H on one input and an
L
on the other,
,
so the output
is
L. At t the input rises to H.
The top input of the gate will rise to V + H,
then the capacitor discharges to
V -
H. At
t2 the input falls to zero.
The voltage across the capacitor can't
change instantaneously, so the top input to
the gate is brought down to V
-
H, which
will be a low level if H is close enough to
V.
The output of the gate rises to an H level.
The capacitor then charges toward V through
Re.*
When the capacitor voltage is greater
than about
1
volt (a high level), the output
falls back to a low. Hence, for an H-to-L
transition
in,
we get
a
pulse of fixed dura-
tion
out.
For the flip-flop to change state, an alter-
nate high level is required between inputs.
Two high levels are not allowed. Even if you
could remove them simultaneously, the re-
sulting state would be indeterminate because
C
of different
I
switching times. However,
during the time two high levels are applied,
both outputs will be low, of course.
The third connection is an OR gate:
+
'
R
The name implies an assignment of posi-
,
tive logic: H
i s
designated
1
but the circuit
is still characterized by the H-L description.
(That is, a low output for two low inputs; a
high output otherwise.) The second gate in-
verts the output of the first. Note that this
circuit is an AND gate if an H level is des-
ignated zero and
L
is designated
1.
is an equivalent resistance that will be a "two-
segment" resistor. I t consists of
R
until the gate
input transistor turns on, then of
R
in parallel with
the gate resistance after turn-on.
The
voltage applied
to the charge path is
Vcc
before the gate turns on,
and
V
after
i t
turns
on.
the
TO
keyer
The
TO
keyer
i s
familiar to most ama-
teurs, but for completeness, its block dia-
gram
is
shown in
fig.
1A.
Clock pulses tog-
gle
FF1
whenever the clock is enabled. When
34
Q
november 1969
1.8-tll,,,,
and
4 3
conducts the saturation
the dot contacts are closed, the clock ant1
FF1
ctrllec-tor current of
Q4.
When the dot or dash
are enabled,
producing
the output as shown
cont,lc
t
is closed, point A goes low, 4 4 is cut
In fig.
16.
When the dash contacts are
close-tl
both
flip-flops
are enabled, and the o11tl~u1
oft,
ant1
Q5
conducts. This reduces the vol-
I ~ K ( > ~ t
point B, which biases
Q3
even more
'
looks llke the waveform In fig.
1C.
Hencc,
t q c
inro conduction, causing more base drive to
have a guaranteed one-to-one dotispace
I J ~ I O
Q5.
7he voltage at point B
is
further re-
and a three-to-one dashldot ratlo Th~s
I.
tl~rcctl. Finally,
C3
is discharged to
the deflnlng characterlst~cof the TO kc')t'r
I/,,,:
VItE,
at which point
Q5
ceases to
Add~tronsto the baslc TO keyer block GIIJ
gram for a dot memory are shown In fig.
2.
con(l~~cThe voltage at point B increases,
t.
When the dot contacts are closed, the rnc,ln
wh~ch
cuts off
Q3
until the capacitor charges
ory
IS
set and the clock and
F F I
are enal)lc~tl
10
1 . 8
V
,
again, then the whole process
Thts causes a dot to be formed Once folnit1tl
~c~l)c'.ils.
Result: nice, fast 1.8
-
VCEsaT
neg-
a pulse from the output resets the menlory
so only
one
dot
IS
sent Wlth the block (II~I
gram rn m~nd,let's look at the cornpletc
clr
fig.
2.
TO
keyer with dot memory added.
cult (fig. 3).
,,.,.
+
-+
toggling voltage
The clock is as described by
K3CULZI.l
When a high level is at point A, Q4 is
S J ~ L I -
rated. Because
VCES.IT
(saturation collcctor-
emitter voltage) is less than
VJIE
(ON
~ J \ C > . -
emitter voltage),
4 5
is
cut off. Point
13
i s
thus at 1.8 volts,
C3
i s
charged
t o
fig.
1.
Basic block diagram of the
TO
keyer,
A,
with dot and dash waveforms,
B
and
C.
CLOCK
FFI
FFI
alive pulses-good for toggling flip-flops.
1-he
PS
and
5
terminals of both flip-flops
atc grounded. There are only two possible in-
put states for the flip-flop: complement (both
S
a n d
C
low) and a low output on terminal 1
(high input on
C).
A flip-flop can be consid-
ctcvl disabled with a high input on
C
and en-
nblcd with a low input on
C,
if complement-
ing
i s
the desired operation.
/\
high input
is
applied to both flip-flops
and
lo the clock (point
A,
fig. 3) when the
keiser
paddle is i n the center, so everything
is rlu~et.
dot
formation
C
Iosrng the dot contact enables the clock,
en,tl)leh the dot flip-flop, and sets the dot
mctntory. Recall that a high-to-low transition
on thc Input of a one-shot gives a pulse out,
anti the terminal 1 output is low when
a
high
voltage
IS
on the top input terminal. Thus,
pcilrlr A is kept low by the memory when set.
The
f~rstclock pulse puts FF1 i n a high
november 1969
Q
35
fig.
3.
Complete schematic of the keyer. Memory end reset cir-
cuits ensure positive dot formation with no omissions.
state, and the high-to-low transition of
FFI's
0
output puts FF2 in a low state, because its
C terminal is high.
The second clock pulse puts
FF1
to a low
state. During this time, the clock remains
enabled because point A is kept low by di-
ode
D8
(this makes the characters self-com-
pleting). Gate 7's output goes low as soon
as the
1
output rises to a high on the first
clock
pulse. Also, the high-to-low transition
at gate 7's output gives
a
reset pulse to the
dot memory. The waveforms for a single dot
are shown i n
fig.
4.
The reset one-shot provides a longer pulse
than the set one-shot. Thus, when they start
at the same time, the memory ends up reset.
The reset pulse length is about
4
ms. Any
shorter pulse would work as well, but
4
ms
i s
long enough to ensure memory reset de-
spite inevitable contact bounce from the
paddle. A series of dots is produced by hold-
ing the dot contacts closed. The wave-forms
in
fig.
4
are then merely repeated, except for
the set pulse.
dash formation
Closing the dash contacts produces a se-
ries of dashes, as with the ordinary TO key-
er. Note that FF2 is enabled or disabled by
an AND gate. (To become enabled, the flip-
flop requires a low input from the gate,
which requires the dash contact output AND
the memory output to be low.) The AND
gate's function will be described later.
dash-dot sequence
Consider
fig.
5 .
Even though the dot con-
tacts were closed and released before the
preceding dash was completed, the dot is
generated. The
low
level from the memory
36
november 1969

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