S805_Datasheet V0.8 20150126.pdf

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S805
Datasheet
Revision: 0.8
Release date: 1/26/2015
Amlogic, Inc.
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S805 Datasheet
Revision 0.8
COPYRIGHT
© 2015 Amlogic, Inc.
All rights reserved. No part of this document may be reproduced. Transmitted, transcribed, or translated into any language in
any form or by any means with the written permission of Amlogic, Inc.
TRADEMARKS
AMLOGIC is a trademark of Amlogic, Inc. All other trademarks and registered trademarks are property of their respective
companies.
DISCLAIMER
Amlogic Inc. may make improvements and/or changes in this document or in the product described in this document at any
time.
This product is not intended for use in medical, life saving, or life sustaining applications.
REVISION HISTORY
Revision
Number
0.8
Revision Date
2015/1/26
Changes
Initial version release
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CONTACT INFORMATION
Amlogic, Inc.
2518 Mission College Blvd, Ste 120
Santa Clara, CA 95054
U.S.A.
www.amlogic.com
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AMLOGIC, Inc. Proprietary
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Circuit diagrams and other information relating to products of Amlogic Inc. are included as a means or illustrating typical
applications. Consequently, complete information sufficient for production design is not necessarily given. Amlogic makes no
representations or warranties with respect to the accuracy or completeness of the contents presented in this document.
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S805 Datasheet
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Contents
Section I
System ........................................................................................................................................................ 6
1. GENERAL DESCRIPTIONS.................................................................................................................................... 7
2. FEATURES SUMMARY ........................................................................................................................................ 8
3. CPU AND GPU SUBSYSTEM .............................................................................................................................. 12
3.1.
Overview................................................................................................................................................... 12
4. MEMORY MAP ................................................................................................................................................. 13
5. POWER DOMAIN.............................................................................................................................................. 14
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
Overview................................................................................................................................................... 14
Top Level Power Domains ........................................................................................................................ 16
A5 Power Modes ...................................................................................................................................... 16
EE Top Level Power Modes ...................................................................................................................... 17
Power/Isolation/Memory Power Down Register Summary.................................................................... 18
6. CLOCK AND RESET UNIT................................................................................................................................... 21
6.1.
6.2.
6.3.
6.4.
Overview................................................................................................................................................... 21
Clock Trees................................................................................................................................................ 21
Clock Gating .............................................................................................................................................. 25
Register Description ................................................................................................................................. 28
7. SYSTEM BOOT .................................................................................................................................................. 37
7.1.
7.2.
7.3.
Overview................................................................................................................................................... 37
Power-on Flow Chart ................................................................................................................................ 37
8. GENERAL PURPOSE INPUT/OUTPUT (GPIO) .................................................................................................... 39
8.1.
8.2.
8.3.
8.4.
Overview................................................................................................................................................... 39
GPIO Multiplex Function .......................................................................................................................... 39
GPIO Interrupt .......................................................................................................................................... 45
Register Description ................................................................................................................................. 46
9. INTERRUPT CONTROLLER ................................................................................................................................ 50
9.1.
9.2.
9.3.
10.
Overview................................................................................................................................................... 50
Interrupt Source ....................................................................................................................................... 50
Register Description ................................................................................................................................. 55
DIRECT MEMORY ACCESS CONTROLLER (DMAC) ........................................................................................ 57
Overview ............................................................................................................................................... 57
10.1.
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Power-on Configuration ........................................................................................................................... 38
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Mali Power Modes ................................................................................................................................... 17
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S805 Datasheet
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10.2.
10.3.
10.4.
11.
Descriptor Table.................................................................................................................................... 57
DMA Hardware Algorithm .................................................................................................................... 58
Register Description .............................................................................................................................. 60
TIMER ........................................................................................................................................................... 62
Overview ............................................................................................................................................... 62
Register Definitions............................................................................................................................... 64
11.1.
11.2.
12.
Real Time Clock ............................................................................................................................................ 68
Overview ............................................................................................................................................... 68
Features ................................................................................................................................................ 68
Functional Description .......................................................................................................................... 68
RTC Peripheral Register Description ..................................................................................................... 70
RTC Register Description....................................................................................................................... 71
12.1.
12.2.
12.3.
12.4.
12.5.
Section II
13.
MMC/SD/SDIO CONTROLLER ....................................................................................................................... 74
Overview ............................................................................................................................................... 74
Features ................................................................................................................................................ 74
Functional Description .......................................................................................................................... 74
Timing Specification .............................................................................................................................. 75
Register Description .............................................................................................................................. 76
13.1.
13.2.
13.3.
13.4.
13.5.
14.
INTER-INTEGRATED CIRCUIT (I2C) ................................................................................................................ 79
14.2.
14.3.
14.4.
15.
Features ................................................................................................................................................ 79
Register Description .............................................................................................................................. 80
SERIAL PERIPHERAL INTERFACE COMMUNICATION CONTROLLER.............................................................. 83
15.1.
15.2.
15.3.
15.4.
15.5.
16.
16.1.
16.2.
16.3.
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Overview ............................................................................................................................................... 83
Features ................................................................................................................................................ 83
Functional Description .......................................................................................................................... 83
Timing Specification .............................................................................................................................. 85
Register Description .............................................................................................................................. 86
SERIAL PERIPHERAL INTERFACE FLASH CONTROLLER .................................................................................. 89
Overview ............................................................................................................................................... 89
Features ................................................................................................................................................ 89
Timing Specification .............................................................................................................................. 89
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Timing Specification .............................................................................................................................. 79
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14.1.
Overview ............................................................................................................................................... 79
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INTERFACE ............................................................................................................................................ 73
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S805 Datasheet
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16.4.
17.
Register Description .............................................................................................................................. 90
UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER ...................................................................... 97
Overview ............................................................................................................................................... 97
Features ................................................................................................................................................ 97
Functional Description .......................................................................................................................... 98
Register Description .............................................................................................................................. 99
17.1.
17.2.
17.3.
17.4.
18.
INFRARED REMOTE .................................................................................................................................... 101
Overview ............................................................................................................................................. 101
Decoder Functional Description ......................................................................................................... 101
NEC Infrared Transmission Protocol Example .................................................................................... 102
Register Description ............................................................................................................................ 104
18.1.
18.2.
18.3.
18.4.
19.
UNIVERSAL SERIAL BUS .............................................................................................................................. 111
19.2.
20.
Features .............................................................................................................................................. 111
PULSE-WIDTH MODULATION ..................................................................................................................... 112
Overview ............................................................................................................................................. 112
Register Description ............................................................................................................................ 113
20.1.
20.2.
21.
SAR ADC ..................................................................................................................................................... 114
Overview ............................................................................................................................................. 114
Register Description ............................................................................................................................ 115
21.1.
21.2.
22.
22.1.
22.2.
22.3.
22.4.
Overview ............................................................................................................................................. 120
Timing Specification ............................................................................................................................ 121
Register Description ............................................................................................................................ 122
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Features .............................................................................................................................................. 120
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ETHERNET MAC .......................................................................................................................................... 120
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19.1.
Overview ............................................................................................................................................. 111
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