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Embedded Intel486
™
Processor
Hardware Reference Manual
Release Date: July 1997
Order Number: 273025-001
The embedded Intel486™ processors may contain design defects known as errata which may
cause the products to deviate from published specifications. Currently characterized errata are
available on request.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth-
erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any
time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing
your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s web site at http:\\www.intel.com
Copyright © INTEL CORPORATION, July 1997
*Third-party brands and names are the property of their respective owners.
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1
MANUAL CONTENTS ................................................................................................... 1-1
1.2
NOTATIONAL CONVENTIONS..................................................................................... 1-3
1.3
SPECIAL TERMINOLOGY ............................................................................................ 1-4
1.4
ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-5
1.4.1
FaxBack Service ........................................................................................................1-5
1.4.2
World Wide Web ........................................................................................................1-5
1.5
TECHNICAL SUPPORT ................................................................................................ 1-5
1.6
PRODUCT LITERATURE.............................................................................................. 1-6
1.6.1
Related Documents ...................................................................................................1-6
CHAPTER 2
INTRODUCTION
2.1
PROCESSOR FEATURES............................................................................................ 2-2
2.2
Intel486™ PROCESSOR PRODUCT FAMILY.............................................................. 2-4
2.2.1
Operating Modes and Compatibility ...........................................................................2-5
2.2.2
Memory Management ................................................................................................2-5
2.2.3
On-chip Cache ...........................................................................................................2-6
2.2.4
Floating-Point Unit .....................................................................................................2-6
2.2.5
Upgrade Power Down Mode ......................................................................................2-7
2.3
SYSTEM COMPONENTS ............................................................................................. 2-7
2.4
SYSTEM ARCHITECTURE ........................................................................................... 2-7
2.4.1
Single Processor System ...........................................................................................2-8
2.4.2
Loosely Coupled Multi-Processor System .................................................................2-9
2.4.3
External Cache ........................................................................................................2-10
2.5
SYSTEMS APPLICATIONS......................................................................................... 2-11
2.5.1
Embedded Personal Computers ..............................................................................2-12
2.5.2
Embedded Controllers .............................................................................................2-12
iii
EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
CHAPTER 3
INTERNAL ARCHITECTURE
3.1
INSTRUCTION PIPELINING ......................................................................................... 3-6
3.2
BUS INTERFACE UNIT................................................................................................. 3-7
3.2.1
Data Transfers ...........................................................................................................3-8
3.2.2
Write Buffers ..............................................................................................................3-8
3.2.3
Locked Cycles............................................................................................................3-9
3.2.4
I/O Transfers ..............................................................................................................3-9
3.3
CACHE UNIT ............................................................................................................... 3-10
3.3.1
Cache Structure .......................................................................................................3-10
3.3.2
Cache Updating .......................................................................................................3-12
3.3.3
Cache Replacement ................................................................................................3-12
3.3.4
Cache Configuration ................................................................................................3-12
3.4
INSTRUCTION PREFETCH UNIT............................................................................... 3-13
3.5
INSTRUCTION DECODE UNIT................................................................................... 3-14
3.6
CONTROL UNIT .......................................................................................................... 3-14
3.7
INTEGER (DATAPATH) UNIT ..................................................................................... 3-14
3.8
FLOATING-POINT UNIT ............................................................................................. 3-15
3.8.1
IntelDX2™ and IntelDX4™ Processor On-Chip Floating-Point Unit ........................3-15
3.9
SEGMENTATION UNIT............................................................................................... 3-15
3.10 PAGING UNIT ............................................................................................................. 3-16
CHAPTER 4
BUS OPERATION
4.1
DATA TRANSFER MECHANISM .................................................................................. 4-1
4.1.1
Memory and I/O Spaces ............................................................................................4-1
4.1.1.1
Memory and I/O Space Organization ....................................................................4-2
4.1.2
Dynamic Data Bus Sizing ..........................................................................................4-3
4.1.3
Interfacing with 8-, 16-, and 32-Bit Memories ............................................................4-5
4.1.4
Dynamic Bus Sizing During Cache Line Fills .............................................................4-9
4.1.5
Operand Alignment ..................................................................................................4-10
4.2
BUS ARBITRATION LOGIC ........................................................................................ 4-12
4.3
BUS FUNCTIONAL DESCRIPTION ............................................................................ 4-15
4.3.1
Non-Cacheable Non-Burst Single Cycle ..................................................................4-16
4.3.1.1
No Wait States ....................................................................................................4-16
4.3.1.2
Inserting Wait States ...........................................................................................4-17
4.3.2
Multiple and Burst Cycle Bus Transfers ...................................................................4-17
4.3.2.1
Burst Cycles ........................................................................................................4-18
4.3.2.2
Terminating Multiple and Burst Cycle Transfers .................................................4-19
4.3.2.3
Non-Cacheable, Non-Burst, Multiple Cycle Transfers.........................................4-19
4.3.2.4
Non-Cacheable Burst Cycles ..............................................................................4-20
4.3.3
Cacheable Cycles ....................................................................................................4-21
4.3.3.1
Byte Enables during a Cache Line Fill ................................................................4-22
iv
CONTENTS
4.3.3.2
Non-Burst Cacheable Cycles ..............................................................................4-23
4.3.3.3
Burst Cacheable Cycles......................................................................................4-24
4.3.3.4
Effect of Changing KEN# during a Cache Line Fill..............................................4-25
4.3.4
Burst Mode Details...................................................................................................4-26
4.3.4.1
Adding Wait States to Burst Cycles ....................................................................4-26
4.3.4.2
Burst and Cache Line Fill Order..........................................................................4-27
4.3.4.3
Interrupted Burst Cycles......................................................................................4-28
4.3.5
8- and 16-Bit Cycles.................................................................................................4-29
4.3.6
Locked Cycles..........................................................................................................4-31
4.3.7
Pseudo-Locked Cycles ............................................................................................4-32
4.3.7.1
Floating-Point Read and Write Cycles ................................................................4-33
4.3.8
Invalidate Cycles ......................................................................................................4-33
4.3.8.1
Rate of Invalidate Cycles ....................................................................................4-35
4.3.8.2
Running Invalidate Cycles Concurrently with Line Fills.......................................4-35
4.3.9
Bus Hold ..................................................................................................................4-38
4.3.10 Interrupt Acknowledge .............................................................................................4-40
4.3.11 Special Bus Cycles ..................................................................................................4-41
4.3.11.1 HALT Indication Cycle.........................................................................................4-41
4.3.11.2 Shutdown Indication Cycle ..................................................................................4-41
4.3.11.3 Stop Grant Indication Cycle ................................................................................4-41
4.3.12 Bus Cycle Restart ....................................................................................................4-43
4.3.13 Bus States................................................................................................................4-45
4.3.14 Floating-Point Error Handling for the IntelDX2™ and IntelDX4™ Processors.........4-46
4.3.14.1 Floating-Point Exceptions ...................................................................................4-46
4.3.15 IntelDX2™ and IntelDX4™ Processors Floating-Point Error Handling
in AT-Compatible Systems.......................................................................................4-47
4.4
ENHANCED BUS MODE OPERATION (WRITE-BACK MODE)
FOR THE WRITE-BACK ENHANCED IntelDX4™ PROCESSOR4-50
4.4.1
Summary of Bus Differences ...................................................................................4-50
4.4.2
Burst Cycles .............................................................................................................4-50
4.4.2.1
Non-Cacheable Burst Operation .........................................................................4-51
4.4.2.2
Burst Cycle Signal Protocol.................................................................................4-51
4.4.3
Cache Consistency Cycles ......................................................................................4-52
4.4.3.1
Snoop Collision with a Current Cache Line Operation ........................................4-54
4.4.3.2
Snoop under AHOLD ..........................................................................................4-54
4.4.3.3
Snoop During Replacement Write-Back..............................................................4-59
4.4.3.4
Snoop under BOFF# ...........................................................................................4-61
4.4.3.5
Snoop under HOLD.............................................................................................4-64
4.4.3.6
Snoop under HOLD during Replacement Write-Back .........................................4-66
4.4.4
Locked Cycles..........................................................................................................4-67
4.4.4.1
Snoop/Lock Collision...........................................................................................4-68
4.4.5
Flush Operation .......................................................................................................4-69
4.4.6
Pseudo Locked Cycles ............................................................................................4-70
4.4.6.1
Snoop under AHOLD during Pseudo-Locked Cycles..........................................4-70
4.4.6.2
Snoop under Hold during Pseudo-Locked Cycles...............................................4-71
4.4.6.3
Snoop under BOFF# Overlaying a Pseudo-Locked Cycle ..................................4-72
v

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