SAA5281ZP(1).pdf

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INTEGRATED CIRCUITS
DATA SHEET
SAA5281
Integrated Video input processor
and Teletext decoder (IVT1.8*)
Preliminary specification
Supersedes data of June 1994
File under Integrated Circuits, IC02
1996 Nov 04
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
FEATURES
•
Complete Teletext and VPS decoding in a single
package
•
Built-in 8K
×
8 memory for up to 8 page storage
•
Enhanced mode allows 7 Fastext pages and 8 pages of
TOP to be captured
•
Ability to request only subtitle pages
•
Acquisition and decoding of VPS data
•
Data valid output available to indicate reception of
error-free VPS or packet 8/30/2 data
•
Software and hardware compatible with SAA5246 and
SAA5248
•
Meshing display within boxes
•
Separate data checking algorithms and pointers for
each acquisition channel
•
24 : 18 Hamming checker
•
Automatic packet 26 extension character processing
•
Indication of Line 23 for external use
•
13.5 MHz clock output to drive external microcontroller
•
Detection of Spanish transmissions to disable
flicker-stopper
•
Compatible with Philips’ one-chip TV IC (TDA836X) for
scan-locking applications.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
V
sync
V
vid(p-p)
f
xtal
T
amb
supply voltage
supply current
sync voltage amplitude
video input voltage amplitude
(peak-to-peak value)
crystal frequency
operating ambient temperature
PARAMETER
4.5
−
0.1
0.7
−
−20
MIN.
5.0
75
0.3
1.0
27
−
TYP.
DESCRIPTION
SAA5281
The IVT1.8* is a single-chip Teletext decoder IC for
decoding 625-line based World System Teletext
transmissions. The device is based on IVT1.0VPS and has
reception facilities for the 5 MHz biphase VPS signal. It is
intended for use in video recorders, in particular to
implement the VPT facility (VCR programming via
Teletext). With suitable software both VPT standards
(EBU PDC System A and System B) can be
accommodated to allow operation from any European VPT
transmission. Automatic processing of packet 26
transmissions is also possible. No external memory is
required as an 8K
×
8 DRAM is included on-chip for up to
8 page storage. An enhanced mode allows 7 Fastext
pages to be stored, with one chapter used to store
extension packets.
MAX.
5.5
150
0.6
1.4
−
+70
V
UNIT
mA
V
V
MHz
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA5281P
SAA5281ZP
SAA5281GP
DIP48
SDIP52
QFP64
DESCRIPTION
plastic shrink dual in-line package; 32 leads (400 mil)
plastic shrink dual in-line package; 52 leads (600 mil)
plastic quad flat package; 64 leads
(lead length 1.95 mm); body 14
×
20
×
2.8 mm
VERSION
SOT240-1
SOT247-1
SOT319-2
1996 Nov 04
2
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
BLOCK DIAGRAM
SAA5281
handbook, full pagewidth
V DD1
VDD2
BLAN RGBREF
Y
COR
R
22
19
20
18
15
G
16
B
17
DRAM
REFRESH
AND
TIMING
1
10
POWER-ON
RESET
DISPLAY
8K x 8
DRAM
ODD/EVEN
(or DV)
21
24 TO 18
HAMMING
DECODER
PACKET 26
PROCESSING
ENGINE
MEMORY
INTERFACE
TELETEXT
AQUISITION
AND DECODING
VPS
ACQUISITION
AND
DECODING
24
I
2
C-BUS
INTERFACE
23
SDA
SCL
SERIAL-TO
-PARALLEL
CONVERTER
44
SAA5281
TIMING
CHAIN
LINE 23
DATA SLICER
AND CLOCK
REGENERATOR
TELETEXT
OR
VPS CONTROL
DISPLAY CLOCK
PHASE-LOCKED
LOOP
13
11
VCR/FFB
REF
6
37
9
ANALOG
REFERENCE
GENERATOR
ANALOG
TO
DIGITAL
CONVERTER
25
8
CVBS
INPUT
CLAMP
AND SYNC
SEPARATOR
7
BLACK
ANALOG
OUTPUT
BUFFER
27 MHz
CLOCK
GENERATOR
4
POL
CLK O/P
IREF
OSCGND
5
14
12
STTV/LFB
36
2
3
MBD783
V SS1 VSS2
V SS3
CLK EN
OSCIN
OSCOUT
Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).
1996 Nov 04
3
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
PINNING
PIN
SYMBOL
SOT240-1 SOT247-1 SOT319-2
V
DD1
OSCOUT
OSCIN
OSCGND
V
SS1
REF+
BLACK
CVBS
IREF
V
DD2
POL
STTV/LFB
VCR/FFB
V
SS2
R
G
B
RGBREF
BLAN
COR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
52
1
2
3
4 and 5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
11
13
14
15
16
18
19
20
21
22
23
24
27
28
30
32
33
34
35
36
+5 V supply 1
27 MHz crystal oscillator output
27 MHz crystal oscillator input
0 V crystal oscillator ground
0 V ground
DESCRIPTION
SAA5281
positive reference voltage for ADC; this pin should be connected
to ground via a 100 nF capacitor
video black level storage input/output; this pin should be
connected to ground via a 100 nF capacitor
composite video input; a positive-going 1 V (peak-to-peak) input
is required, connected via a 100 nF capacitor
reference current input, connected to ground via a 27 kΩ resistor
+5 V supply 2
STTV/LFB/FFB polarity selection input
sync to TV output line flyback input; function controlled by an
internal register bit (scan sync mode)
PLL time constant switch/field input; function controlled by an
internal register bit (scan sync mode)
0 V ground; connected to V
SS1
for normal operation
dot rate character output of the RED colour information
dot rate character output of the GREEN colour information
dot rate character output of the BLUE colour information
input DC voltage to define the output high level on the RGB pins
dot rate fast blanking output
programmable output to provide contrast reduction of the TV
picture for mixed text and picture displays or when viewing
newsflash/subtitle pages;
open-drain output
in ODD/EVEN mode a 25 Hz output synchronized with the CVBS
input field sync pulses to produce a non-interlaced display by
adjustment of the vertical deflection currents; in DV mode a VPT
data valid signal is used to indicate reception of error-free VPS or
8/30 format 2 data
dot rate character output of teletext foreground colour information;
open-drain output
serial clock input for I
2
C-bus; it can still be driven HIGH during
power-down of the device
serial data port for the I
2
C-bus, open-drain output; it can still be
driven HIGH during power-down of the device
0 V ground
ODD/EVEN
(or DV)
21
22
37
Y
SCL
SDA
V
SS3
22
23
24
25
23
24
25
26
38
39
40
44
1996 Nov 04
4
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
PIN
SYMBOL
SOT240-1 SOT247-1 SOT319-2
i.c.
26 to 35,
38 to 43,
45 to 48
27 to 32,
35 to 38,
41 to 46,
48 to 51
39
40
47
7, 33, 34
1 to 3,
5 to 8,
45 to 53,
55, 61,
63 to 64
56
59
4
internally connected; normally open-circuit
DESCRIPTION
SAA5281
CLK EN
CLK O/P
LINE 23
n.c.
36
37
44
−
clock enable input to enable the clock output (CLP O/P pin 37);
internal pull-down normally disables clock
13.5 MHz clock output to drive an external microcontroller
output for indication of Line 23 for use with external circuitry
9, 10, 12, not connected; normally open-circuit
17, 25, 26,
29, 31,
41 to 43,
54, 57, 58,
60, 62
1996 Nov 04
5

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