webpack-3_1.pdf

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XESS CORPORATION - WWW.XESS.COM
©2000 BY XESS CORP.
Introduction to WebPACK 3.1
Using XILINX WebPACK Software to Create
CPLD Designs
RELEASE DATE: 8/28/2000
XESS CORPORATION - WWW.XESS.COM
©2000 BY XESS CORP.
All XS-prefix product designations are trademarks of XESS Corp.
All XC-prefix product designations are trademarks of Xilinx.
INTRODUCTION TO WEBPACK 3.1
XESS CORPORATION - WWW.XESS.COM
©2000 BY XESS CORP.
Table of Contents
What This Is and
Is Not..............................................................
1
CPLD Programming ................................................................... 3
Installing WebPACK................................................................... 5
Getting WebPACK .......................................................... 5
Installing WebPACK ....................................................... 6
Getting XSTOOLs ........................................................... 7
Installing XSTOOLs ........................................................ 7
Our First Design.......................................................................... 8
An LED Decoder............................................................. 8
Starting WebPACK Project Navigator........................... 10
Naming Your Project..................................................... 16
Describing Your Design With VHDL ............................. 18
Checking the VHDL Syntax .......................................... 26
Fixing VHDL Errors ....................................................... 27
Synthesizing the Logic circuitry for Your Design ........... 28
Fitting the Logic Circuitry Into the CPLD ....................... 29
Checking the Fit ............................................................ 31
Constraining the Fit....................................................... 33
Viewing the Chip ........................................................... 39
Generating the Bitstream .............................................. 45
Downloading the Bitstream ........................................... 51
Testing the Circuit ......................................................... 53
Hierarchical Design................................................................... 54
A Displayable Counter .................................................. 54
I
INTRODUCTION TO WEBPACK 3.1
XESS CORPORATION - WWW.XESS.COM
©2000 BY XESS CORP.
Starting a New Design .................................................. 55
Adding the LED Decoder .............................................. 57
Adding a Counter.......................................................... 60
Tying Them Together ................................................... 66
Checking the VHDL Syntax .......................................... 70
Constraining the Design................................................ 72
Synthesizing the Logic Circuitry for the Design............. 73
Fitting the Logic Circuitry Into the CPLD ....................... 74
Checking the Fit ............................................................ 76
Checking the Timing ..................................................... 78
Generating the Bitstream .............................................. 80
Downloading the Bitstream ........................................... 84
Testing the Circuit ......................................................... 85
Going Further…........................................................................ 86
INTRODUCTION TO WEBPACK 3.1
II

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