1994_ARMv7_instructions_set.pdf

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ARM7DI
Data Sheet
Document Number: ARM DDI 0027D
Issued: Dec 1994
Copyright Advanced RISC Machines Ltd (ARM) 1994
All rights reserved
Proprietary Notice
ARM, the ARM Powered logo, BlackICE and ICEbreaker are trademarks of Advanced RISC
Machines Ltd.
Neither the whole nor any part of the information contained in, or the product described in, this
datasheet may be adapted or reproduced in any material form except with the prior written
permission of the copyright holder.
The product described in this datasheet is subject to continuous developments and
improvements. All particulars of the product and its use contained in this datasheet are given by
ARM in good faith. However, all warranties implied or expressed, including but not limited to
implied warranties or merchantability, or fitness for purpose, are excluded.
This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not
be liable for any loss or damage arising from the use of any information in this datasheet, or any
error or omission in such information, or any incorrect use of the product.
Change Log
Issue
A
B
C
D
Date
July 1994
Aug 94
Oct 94
Dec 94
By
EH
BJH
EH
PB
Change
Created.
Updated Instruction Cycle Operations
Sources repaired: no material changes to text
Edited.
ARM
Advanced RISC Machines
Preface
The ARM7DI is a low-power, general purpose 32-bit RISC microprocessor with integrated debug support.
It comprises the ARM7D CPU core, and ICEbreaker module and a TAP controller. Its simple, elegant and
fully static design is particularly suitable for cost and power sensitive applications.
Enhancements
The ARM7DI is similar to the ARM6 but with the following enhancements:
s
s
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advanced debug (integrated ICE) support for faster time to market
fabrication on a sub-micron process for increased speed and reduced power consumption
3V operation, for very low power consumption, as well as 5V operation for system compatibility
higher clock speedfor faster program execution.
32-bit RISC processor (32-bit data & address bus)
Advanced debug
fully integrated ICE
Address Register
Feature Summary
s
s
s
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Big and Little Endian operating modes
High performance RISC
Low power consumption
Fully static operation
ideal for power-sensitive applications
Address
Incrementer
Instruction
Decoder
&
Logic
Control
Register Bank
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Fast interrupt response
for real-time applications
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Virtual Memory System Support
Excellent high-level language support
Simple but powerful instruction set
D
e
b
u
g
Booth’s
Multiplier
Barrel
Shifter
32 bit ALU
Instruction
Pipeline &
Read Data
Register
Write Data Register
ICEbreaker
TAP controller
Applications
The ARM7DI is ideally suited to those applications requiring RISC performance from a compact,
power-efficient processor. These include:
Telecomms
GSM terminal controller
Datacomms
Protocol conversion
Portable Computing
Palmtop computer
Portable InstrumentS
Handheld data acquisition unit
Automotive
Engine management unit
Information Systems
Smart cards
Imaging
JPEG controller
iv
ARM7DI Data Sheet
Table of Contents
1.0
Introduction
1.1
1.2
1.3
ARM7DI Block Diagram
ARM7D Core Diagram
ARM7DI Functional Diagram
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6
7
8
2.0
3.0
Signal Description
Programmer's Model
3.1
3.2
3.3
3.4
3.5
Hardware Configuration Signals
Operating Mode Selection
Registers
Exceptions
Reset
Instruction Set Summary
The Condition Field
Branch and Branch with link (B, BL)
Data processing
PSR Transfer (MRS, MSR)
Multiply and Multiply-Accumulate (MUL, MLA)
Single data transfer (LDR, STR)
Block Data Transfer (LDM, STM)
Single data swap (SWP)
Software interrupt (SWI)
Coprocessor data operations (CDP)
Coprocessor data transfers (LDC, STC)
Coprocessor register transfers (MRC, MCR)
Undefined instruction
Instruction Set Examples
Cycle types
Byte addressing
Address timing
Memory management
Locked operations
Stretching access times
The External Data Bus
Interface signals
Data transfer cycles
Register transfer cycle
Privileged instructions
Idempotency
Undefined instructions
Overview
Debug Systems
Debug Interface Signals
9
15
15
16
17
20
24
4.0
Instruction Set
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
25
25
26
27
29
36
40
42
48
55
57
59
61
64
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67
5.0
Memory Interface
5.1
5.2
5.3
5.4
5.5
5.6
5.7
71
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72
74
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76
6.0
Coprocessor Interface
6.1
6.2
6.3
6.4
6.5
6.6
81
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83
7.0
Debug Interface
7.1
7.2
7.3
85
85
85
86
i
ARM7DI Data Sheet
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
Scan Chains and JTAG Interface
Reset
Pullup Resistors
Instruction Register
Public Instructions
Test Data Registers
ARM7DI Core Clocks
Determining the Core and System State
The PC's Behaviour During Debug
Priorities / Exceptions
Scan Interface Signals
The Watchpoint Registers
The Debug Control Register
Debug Status Register
Coupling Breakpoints and Watchpoints
Disabling ICEbreaker
ICEbreaker Timing
ICEBreaker Programming Restriction
Branch and branch with link
Data Operations
Multiply and multiply accumulate
Load register
Store register
Load multiple registers
Store multiple registers
Data swap
Software interrupt and exception entry
Coprocessor data operation
Coprocessor data transfer (from memory to coprocessor)
Coprocessor data transfer (from coprocessor to memory)
Coprocessor register transfer (Load from coprocessor)
Coprocessor register transfer (Store to coprocessor)
Undefined instructions and coprocessor absent
Unexecuted instructions
Instruction Speed Summary
Absolute Maximum Ratings
DC Operating Conditions:
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99
100
103
105
106
8.0
The ARM7DI ICEBreaker Module
8.1
8.2
8.3
8.4
8.5
8.6
8.7
109
110
115
116
119
120
120
120
9.0
Instruction Cycle Operations
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
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124
125
127
127
128
129
129
131
132
132
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134
10.0
DC Parameters
10.1
10.2
137
137
137
11.0
12.0
AC Parameters
Appendix - Backward Compatibility
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ii
Introduction
1.0 Introduction
The ARM7DI is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit
microprocessors, which offer very low power consumption and price for high performance devices. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler in comparison with microprogrammed Complex Instruction
Set Computers. This results in a high instruction throughput and impressive real-time interrupt response
from a small and cost-effective chip.
The instruction set comprises eleven basic instruction types:
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•
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•
Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
Three classes of instruction control data transfer between memory and the registers, one optimised
for flexibility of addressing, another for rapid context switching and the third for swapping data;
Three instructions control the flow and privilege level of execution; and
Three types are dedicated to the control of external coprocessors which allow the functionality of
the instruction set to be extended off-chip in an open and uniform way.
The ARM instruction set is a good target for compilers of many different high-level languages. Where
required for critical code segments, assembly code programming is also straightforward, unlike some RISC
processors which depend on sophisticated compiler technology to manage complicated instruction
interdependencies.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
being fetched from memory.
The memory interface has been designed to allow the performance potential to be realised without
incurring high costs in the memory system. Speed critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these control signals facilitate the
exploitation of the fast local access modes offered by industry standard dynamic RAMs.
ARM7DI has a 32 bit address bus. All ARM processors share the same instruction set, and ARM7DI can be
configured to use a 26 bit address bus for backwards compatibility with earlier processors.
ARM7DI is a fully static CMOS implementation of the ARM which allows the clock to be stopped in any
part of the cycle with extremely low residual power consumption and no loss of state.
Notation:
0x
BOLD
binary
- marks a Hexadecimal quantity
- external signals are shown in bold capital letters
- where it is not clear that a quantity is binary it is followed by the word binary
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