HK80_V960E_VME_80960_Users_Manual_Jul90.pdf

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USER'S MANUAL
RevisionE
July
1990
HK80N960E
VMEbus Single-Board Computer
HElRIK9N
~
OPEN
SYSTEMS::OPEN
TOOLS
HK80N960E
VMEbus Single-Board Computer
USER'S MANUAL
RevisionE
july
1990
OPEN SYSTEMS::OPEN TOOLS
The information in this manual has been checked and is believed to be accurate and
reliable. HOWEVER. NO RESPONSIBILIlY IS ASSUMED BY HEURIKON FOR ITS USE
OR FOR ANY INACCURACIES. Specifications are subject to change without notice.
HEURIKON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER
APPLICATION OF ANY PRODUCT, CIRCUIT OR PROGRAM DESCRIBED HEREIN. This
document does not convey any license under Heurikon's patents or the rights of others.
Heurikon is a registered trademark of Heurikon Corporation. Intel is a trademark of Intel
Corporation. Ethernet is a trademark of Xerox Corporation. UNIX is a registered
trademark of AT&T. VxWorks is a trademark of Wind River Systems, Inc.
REVISION HISTORY
Revision
Level
A (Preliminary)
B (Preliminary)
C (Preliminary)
Principal Changes
First publication
Expanded text and
added illustrations
Added power
requirements and
clarified text.
Extensive revision for
release to production.
Added Appendix C.
Date of
Publication
November 1989
December 1989
January 1990
Board
Revision
EP1
EP1,EP2
EP1,EP2
80960CA
Level
D
E
June 1990
July 1990
P
P
A4
B1
Copyright 1990 Heurikon Corporation. All rights reserved. Portions copyright
Intel Corporation 1989. Used with permission.
ii
HK80N960E
User's Manual
Table of Contents
1
-
Overview
1.1
Introduction
1.2
Features
1.3
Block Diagram
1.4 Component Map
1.5
Bus Summary
1.6 Jumpers, Connectors, and Switches
1.6.1
Jumpers
1.6.2
Connectors
1.6.3
Reset
1.7 Overview of the Manual
1.7.1
Terminology and Notation
1.7.2
Additional Technical Information
Getting Started
2.1
Equipment
2.2
Preliminary Considerations
2.2.1
Electrical
2.2.2
Physical
2.2.3
Environmental
2.3
Installation and Power-up
2.4 Troubleshooting and Service Information
2.5
Monitor Summary
MPU Summary Information
Introduction
3.1
3.2 MPU Initialization
Initialization Boot Record (IBR)
3.2.1
Process Control Block (PReB)
3.2.2
Byte Ordering
3.3
3.4 MPU Interrupts
Interrupt Structures
3.4.1
3.4.1.1 The Interrupt Table
3.4.1.2 The Interrupt Stack Frame
3.4.2
The Nonmaskable Interrupt (NMI)
Hardware Interrupts
3.4.3
1-1
1-1
1-3
1-4
1-5
1-6
1-6
1-7
1-7
1-7
1-7
1-7
2
-
2-1
2-2
2:'2
2-2
2-2
2-2
2-3
2-5
3
-
3-1
3-1
3-2
3-2
3-4
3-5
3-5
3-5
3-6
3-6
3-7
Revision E
I
July 1990
iii
3.5
3.6
3.4.4
MPU
3.5.1
3.5.2
MPU
3.6.1
3.6.2
3.6.3
3.6.4
3.7 MPU
3.8 MPU
3.8.1
3.8.2
3.8.3
3.9 MPU
3.10 MPU
4
-
Interrupt Priority
Interrupt Mask Register (IMSK)
Interrupt-Pending Register (IPND)
Interrupt Mapping Registers
(IMAPO-IMAP 2)
3.4.3.5 Interrupt Control Register (ICON)
Software Interrupts
Faults
The Fault Table
The Fault Stack Frame
DMA Support
HK80/v96oE Implementation
Registers/Instructions
3.6.2.1 DMA Command Register (DMAC)
3.6.2.2 The Set-up-DMA (sdma) Instruction
3.6.2.3 Update DMA-Channel RAM Instruction
(udma)
DMA Interrupts
DMA Data Alignment
Trace Events
Caches
Data
RAM
Cache
Instruction Cache
Register Cache
Processing Modes
Register Summary
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3-10
3-11
3-11
3-11
3-13
3-13
3-14
3-14
3-15
3-16
3-17
3-18
3-18
3-18
3-18
3-19
3-19
3-20
3-21
3-21
3-21
3-22
3-22
3-22
System Error Handling
4.1
Introduction
4.2 Error Conditions
4.2.1
Hardware Errors
4.2.2
Software Errors
On-card Memory Configuration
5.1
Introduction
5.2 ROM
5.3 On-card
RAM
5.4 Bus Memory
5.5 Physical Memory Map
5.6 Memory Timing
5.7 Nonvolatile
RAM
VMEbus Control
6.1
Introduction
6.2 VMEbus Signal DeSCriptions
6.3 VIC Register Map
4-1
4-1
4-1
4-2
5
-
5-1
5-1
5-3
5-3
5-4
5-5
5-6
6
-
6-1
6-2
6-5
iv
HK80N960E User's Manual

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