W215_W218_Block_Diagram_Signal_Description.pdf

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W215/W218 EU band Block Diagram Signak Description
Signal Name
A/D[0..15] U101
A[16..23] U101
AUDAMP_SD
AUXI/FM_ROUT
BATTEMP
BS1
CAM_DATA[0..7]
CDI
CDO
From
CKEN
CKM
CLK13M
CLK32K
COL[0..4]/ROW[0..4]
CSCLK
CSYNC
U101
R131/U202
U103
U101
J901
U103
U101
U103
U101
U101
U103`
U101
U101
U01 U103
U101
U103
U103
U101
J602
U202
R202
U101
U101
U101
U603
C112
U103
U103
U103
U101
R201
U101
U701
U101
U103
C607
C601
R618/R620
U101
U101
U7 U10/U108
U101
U101
U101
U101
U103
J901
U101
To
U301
U301
U601
U103
R713
U201
U902
U101
U103
U101
U301
U103
U101
Keypad Matrix
U103
TP1
Voice Receiver
Voice Receiver
U301
C222
U103
U201
U604
J602
U605/U602
U101
U103
C623
C626
U502
R710
U201
LCM
LCM
U701
R601
U103
U103
U103
U301
U301
U301
U301
U301
U201
R501
U902
U301
U101
Signal Description
Address and data bus inputs/outputs multiplexed
Address bus outputs multiplexed
Enable pin of audio amplifier
Headset Microphone/FM radio input (R channel)
NTR connect of the Battery
PA output ( 0 : GSM ; 1: DCS )
Camera Module: Camera Data Bus
AUDIO CODEC port interface serial data input
AUDIO CODEC port interface serial data output
13Mhz clock Enable
Synchronizes the memory to the frequency of the EMIF during synchronous operations such as
burst mode.
13Mhz clock
32Khz clock
Forms part of Keypad Matrix
AUDIO CODEC port interface serial clock
AUDIO CODEC port interface frame synchro
CTS_MODEM
EARN
EARP
FDP
FM_ANT
FM_LOUT
HB_IN
HS_BIAS
HS_DETECT
HS_EN
HS_HOOK
HSMIC
HSOL
HSOR
ICTLAC1
KEY_BL
LB_IN
LCM_RESET
LED+
LEDLCM_EN
MICBIAS
MICIN
MICIP
MODE_DETECT
nBHE
nBLE
nFADV
nFOE
nSC0
nSC3
PA_EN
PCHGAC
PCLK
RNW
RPWON S802
Clear To Send
Negative Audio Voice to Receiver
Positive Audio Voice to Receiver
The Flashreset/deeppower-downmode control
FM Antenna
FM radio input(L channel)
TX VCO generated transmit DCS Frequency
Enable pin of the eadset microphone bias
Headset Detection
Analog switch control(MODEM or Headset)
Handset send/end key detection
Headset Microphone amplifier input (single ended)
Headset 32 ohm driver (L channel)
Headset 32 ohm driver (R channel)
Charge current control signal
When this signal goes high, the Keypad backlights are illuminated
TX VCO generated transmit GSM Frequency
LCM reset pin
LCM BackLight LED driver
LCM BackLight LED Enable
Microphone bias supply(2V)
Negative analogue uplink audio from on board Microphone
Positive analogue uplink audio from on board Microphone
EarJack function detection
Enable to address High Byte Information
Enable to address Low Byte Information
Indicates to memory device that a valid address is present on the address inputs
Flash and SRAM output Enable - Active Low
Used as Chip Enable for the PSRAM
Used as Chip Enable for the Flash Memory
Chip enable for PowerAmp IC
Battery Pre-charge Path
Camera Module: Pixel clock output
Read and Write - allows information to be wriiten or read from the memory devices
ON button
2007.04.27
Level3Schematics
W215/W218
HansonKo
W215/W218
Rev.1.0
Page1of2
RX_DCSM/RX_DCSP
BF202
RX_EGSMM/RX_EGSMP BF201
RX_MODEM U101
SCL1
U101
SCL2
U101
SCLK
U101
SDA1
U101
SDA2
U101
SENSOR_power_EN
U901
SIO_C
U902
SIO_D
U902
SPI_CLK
U101
SPI_nCS
U101
SPI_SIMO
U101
SPKN/SPKP
U103
SW_HI_TX
U101
SW_LO_TX
U101
TCK
U101
TDI
TP112
TDO
U103
TMS
TP110
TRSTN
TP113
TX_MODEM U101
TXHB/TXLB
U101
USIM_CLK
U101
USIM_IO
U101
USIM_PWCTL
U101
USIM_RST
U101
VAC
U501
VAPC
U101
V_AVDD
U901
VBACKUP
U103`
VBAT J703
VBATS
R503
V_BE_CORE
R907
VCCS
R503
VCHG
J501
VRABB
U103
VREXTH
U103
VREXTL
U103
VRIO
U103
VRMEM
U103
VRMMC
U103
VRPLL
U103
VRRTC
U103
VRSIM
U103
VRUSB
U103
VSYNC
J901
Wait
U101
XCLK
J901
U101
Received DCS Antenna Frequency Signal
U101
Received GSM Antenna Frequency Signal
U607
Receive Data
U103
I2C interface Master serial clock reserved for TriTon Lite Control
U202
I2C interface Master serial clock reserved for FM Control
U902
Serial Clock Input for backend IC or LCM
U103
I2C interface Serial bi-directional data reserved for TriTon Lite Control
U202
I2C interface Serial bi-directional data reserved for FM Control
U902
Camera Enable
J901
Camera Module: SCCB serial interface clock input
J901
Camera Module: SCCB serial interface data I/O
LCM
LCM serial clock
LCM
LCM chip select i output
LCM
LCM serial data master-out
U601
Speaker Audio Amp output
T201
DCS TX enable
T201
GSM TX enable
TP111
CLK of JTAG
U101
Data input of JTAG
TP109
Data output of JTAG
U101
JTAG mode selection
U101
JTAG RESET
U608
Transmit Data
R201
In-phase baseband codec uplink signals
J701
SIM Card Reference Clock
J701
SIM Card I/O Data
J701
SIM Pull-Up power control
J701
SIM Card Reset
U103
Power Supply of Charge system
R206
Automatic Powert Control - Sets the PA output level
J901
Camera Module: Camera module power supply
C106
RTC battery Voltage Back up
U102/U103/U201/U202/R503/U601Battery Voltage for supply purposes
U103
Charging current sense
U902
Regulator for backend IC
U103
Charging current sense
U501
Adaptor DC input
U103
Power supply of U10
U101
For DRP
U101
DBB core voltage
U101/U202/LCM/R623/R631
I/O of the LCM .FM,and U101
U101/U301
For Flash power supply
U101/R211/R213
For RF power supply
U103
DPLL/APLL subchip dedicated power supply inside DBB
U103
Regulator RTC output
J701
For SIM card power supply
TP128
USB power
U902
Camera Module: Vertical sync output
U301
Flash and synchronous PSRAM- specific signal configureable true-level output
U902
Camera Module: System clock input
2007.04.27
Level3Schematics
W215/W218
HansonKo
Rev.1.0
Page2of2
W215/W218

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