Barracuda_Block_diagram.pdf

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A10
U10 / TX
VC1
1
0
VC4
0
1
RX
LOCAL
OSCILLATOR
A9
GSM
DCS
Osc.
discrete
circuty
Q203
800MHz
D8
PLL
VC4
DCS
J100
Mech. Ant Switch
11
1
D101
VC1
RX
Filter
7
2
FL480
1
5
FL472
1805-1880MHz
2
RF_V2
2,3,5,
6,20
RVCO
400 MHz
1
2
5
FL490
CR249
RF_V1
C8
U200
MAGIC
F7
RXI
DEMODULATION
RXQ
10
( SCLK_OUT ) BCLKR
( SDFS ) BFSR
( SDRX ) BDR
to WhiteCap
9
DCS
1
GSM
VC2
2
4
U432
FRONTEND IC
3
16
24
7
B
Q490
C
C
PRE_IN
A7
STEP
ATT.
SWITCH
C7
C6
RX
SPI
G9
G8
925-960MHz
5
SW_VCC
VC1
GSM
RX_EN
DCS_SEL
2,75V
RF_V2
B+
2,75V
RF_V1
3
D2 G2
F1
B+
H1
5 S1
2 S2
6 D1
1
G1
H2
Q201
4
RVCO
F9
G1
PHASE
DET
Divider
200KHz
VRef
REG.
J7
CR248
13MHz
SWITCH
J9
C8,H7;B3
RX VCO MID CHANNELS
GSM: CH 62 -- 1347,4 MHz
EGSM: CH 37 -- 1342,4Mhz
DCS: CH 700 -- 1442,8MHz
2
TX FRQ. RANGE
EGSM: 880-915Mhz
DCS: 1710-1785MHz
RX VCO FRQ. RANGE
EGSM: 1325 - 1360Mhz
DCS: 1405 - 1480MHz
11
RX_LO_OUT
GSM_TX_RF_OUT
DCS_TX_RF_OUT
TX VCO FRQ. RANGE
EGSM: 880-915Mhz
DCS: 1710-1785MHz
TX VCO MID CHANNELS
GSM: CH 62 -- 902,4MHz
EGSM: CH 37 -- 897,4Mhz
DCS: CH 700 -- 1747,8MHz
12
14
16
1
RX / TX
13
2
VCO
4
TX_EN
RVCO
5
3
6
6
SUPER
FILTER
J6
MUX
Startup
Ref.
1 /2
Prog.
Divider
200KHz
REF.
MAGIC_13MHz
CLK_SELCT
to WhiteCap
from WhiteCap
SF_OUT
6
Inverter
Q313
1
Q313
4
3
5
4
Q312
Iso.
Switch
Q312
1
2
GSM_TX_VCO
DCS_TX_VCO
DCS_SEL
TX_EN
C1
A1
B1
A3
G6
PHASE
DET
Divider
AFC
F2
REF. OSC.
26 MHz
PA_B+
6,8
4
2
14
26MHz
Y200
U506 PA
GSM_PA_OUT
10
DCS_PA_OUT
12
U253
TX LOOP
FILTER
V1_SW
C2
PLL
( CE ) MQSPI_CS1
SPI
G5
( SPI_CLK ) MOSPI_CLK1
( SPI_DATA ) DX1
J3
from WhiteCap
LOGIC
CONTROL
INTER
H4
FACE
GP02
C4
T192 (Barracuda)
PAC_275
U501
1
RF_IN
+ -
COMP.
RF DET
3,14
4
5
DCS_SEL
PAC
BUFFER
AMP
(Gain 1or 3)
+ -
SAT.
DET.
-
+
INTEGR.
6
VCTRL
Bias Switch
RF_V2
Q506
PAC_275
Q505
Mute Switch
DM_CS
( SDTX ) BDX
TXI
TX
SPI
J2
( TX_CLK ) BCLKX
G7
MODULATION
TXQ
9 8
10
11 7
if DM_CS is low
VCTRL is pulled to GND
Logic 1 at low power
Logig 0 at high power
AOC_DRIVE
SAT_DETECT
DETECT_SW
TX_KEY_OUT
AOC_DRIVE
SAT_DETECT
DETECT_SW
TX_KEY_OUT
B6
H8
PA
CONTROL
LOGIC
GPRS_TX
J4
CONTROL
H5
RX_ACQ
DM_CS
TX_KEY
from WhiteCap
B4
A5
C5
DCS_SEL
GSM_TX_VCO
DCS_TX_VCO
PAC_275
VC1
VC4
RVCO
RF_V2
TX_EN
DM_CS
RX SIGNAL PATH
GSM SERVICE SUPPORT GROUP
LEVEL 3 RF Block Diagram
T192 ( Barracuda )
Ralf Lorenzen, Michael Hansen, Ray Collins
Page1
12.07.01
Rev. 1.0
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
GSM / DCS SELECT CIRCUIT
KBR0-KBR2
( Keyboard )
KBC0-KBC3
BKLT_EN
DP_EN_L
RSTO
CLKO
SIM_TX
SIM_RX
H2, H1, H3
J5, J3, J2
KEYPAD
K3
DISPLAY
A11
INTERFACE
E9
E7
F3
B5
SIM
INTER
FACE
C4, H4,
WHITE_CAP
C14, F10, K13,K5
P13
U700
VDDS
VCC_MEMIF
VDD
A9,A10, C5, M8, M11
VCCA
G12
( CE ) MQSPI_CS1
N8
SPI
( SPI_CLK ) MOSPI_CLK1
K7
INTERFACE
( SPI_DATA ) DX1
M7
M
E
M
O
R
Y
V2
V3
( MAGIC SPI )
D7 - D0
J902
Display Con.
DATA BUS
A0
15-22
M3
UART
EXTB+_DET
N3
HEAD_INT
L2
BATT_THERM
A1
CLK_SELECT
TX_EN
C1
CTM
DM_CS
E2
MODULE
TX_KEY
E1
RX_EN
E3
RX_ACQ
E4
RESET
E8
( SDTX ) BDX
B6
( TX_CLK ) BCLKX
B3
SERIAL
( SCLK_OUT ) BCLKR
INTER
DSP
from / to MAGIC
B4
( SDFS ) BFSR
FACE
D4
( SDRX ) BDR
A3
DSC_EN
DSC
K2
TP4
ADDRESS BUS
SR_VCC
C9
E10
B11
D9
B9
CE2
CE3
R_W
D6, E1
B2
U702
A1
SRAM
G5
CE0
CE1
V2
RESET
V2
RESET
A4, E1, F5
R_W
DP_EN_L
GND
-5V
KBR0 - KBR2
( WhiteCap )
KBC0 - KBC3
( GCAP2 )
ON_2
23
14,26
24
4
25
1-6,13
15
CPU
I
N
T
E
R
F
A
C
E
U701
EPROM
B3
EEPROM
B4
D7
F8
KEYBOARD
CTM
F1
L7
CHARGE
P6
ENABLE
TRKL_SET
V1
STBY_DL
DEEP SLEEP
CIRCUIT
(Magic)
V1_SW
( GCAP2 )
ALRT_VCC
Q913
BACKLIGHT
Q902
VIB 1
VIB 2
( White Cap )
BKLT_EN
( GCAP2 )
ALRT_VCC
SPI
INTERFACE
TIMER
B7 P4 H10
MAGIC_13MHz
AUDIO SPI
GCAP SPI
GCAP_CLK
13 MHz
GCLK
32.768 KHz
CHARGER
D902
EXT_B+
Q900
U903
R923
B+
B+
BATTERY
CONN.
M901
3,4
VIB_EN
V2
R941
Q901
TP2
B+
V2
BATT_THERM_AD
( GCAP2 )
ISENSE
GND
2,5
RT900
CHARGER JACK
J903
EXT_B+
Q903
Y900
EXTB+_DET
F5
C7 A7 B7
SPI
INTERFACE
MAN_TEST_AD
REAL TIME
CLOCK
LEVEL
SHIFT
F6
J7
J8
K7
G6
K10
H8
D10
ON2
RESET
C4
G5
Logic Control
C8
G4
VREF
REG.
CLK
RESET
SIM_I/O
TRKL_SET
3
2
6
RSTO
CLKO
SIM_TX
SIM_RX
PWR_ON
ON2
STBY_DL
J902
SIM
Con.
1,5
4
8
1
7
2
COVIC
3
6
5
4
PWR_ON
ENABLE
BATT_ID
R944
1,6
VSIM1
Mode
Current
TRKL_SET
ENABLE
Full Rate High Trickel Low Trikel
300mA
Low
High
100mA
High
Low
40mA
Low
Low
Off
<1mA
High
High
T192 (Barracuda)
R931
R605
A1
BATT_ID
BATT_THERM_AD
SENSE
A3
B3
CNTL.
U900
G_CAP2
Q914
BATT_THERM
( White Cap )
TP1
GND
V2
TP5
G9
B5
E1
VREF
2.775V for Magic
V3
1,8V, for WhiteCap
SR_VCC
2.775V, for SRAM
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
V1
5.0V, for DSC Bus, Negative Voltage Regulator
VSIM1
3.0 or 5.0V, for SIM Card Circuit
TP3
TP6
UPLINK
DOWNLINK
J900
MIC
MIC
D2
C3
V3
REG.
J2
PA_DRV
Interface
Audio
Codec
H6 H7 K9 J9
SPR+
V2
REG.
V1
REG.
VSIM
REG.
J5
A6
C6
A10
HEADSET
CON.
J504
1
3
4
2
AUX_MIC
H3
H9
F7
K5 E10
VBOOST1
REG.
B10
SPKR
1,2,5,6 3 4
Q904
L901
D900
Internal GCap use only (VSIM1, LS_V1)
V_BOOST1
C956
ALRT
LS900
IRQ_2
ALRT_VCC
B+
ALRT_VCC
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
SPR-
ALRTOUT
GSM SERVICE SUPPORT GROUP
LEVEL 3 AL Block Diagram
T192 ( Barracuda )
Ralf Lorenzen, Michael Hansen, Ray Collins
12.07.01
Rev. 1.0
Page2

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